2 * dts file for Xilinx ZynqMP
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
6 * Michal Simek <michal.simek@xilinx.com>
8 * SPDX-License-Identifier: GPL-2.0+
11 compatible = "xlnx,zynqmp";
20 compatible = "arm,cortex-a53", "arm,armv8";
22 enable-method = "psci";
27 compatible = "arm,cortex-a53", "arm,armv8";
29 enable-method = "psci";
34 compatible = "arm,cortex-a53", "arm,armv8";
36 enable-method = "psci";
41 compatible = "arm,cortex-a53", "arm,armv8";
43 enable-method = "psci";
49 compatible = "arm,dcc";
55 compatible = "xlnx,zynqmp-genpd";
58 #power-domain-cells = <0x0>;
63 #power-domain-cells = <0x0>;
68 #power-domain-cells = <0x0>;
73 #power-domain-cells = <0x0>;
78 #power-domain-cells = <0x0>;
83 #power-domain-cells = <0x0>;
88 #power-domain-cells = <0x0>;
93 #power-domain-cells = <0x0>;
98 #power-domain-cells = <0x0>;
103 #power-domain-cells = <0x0>;
108 #power-domain-cells = <0x0>;
113 #power-domain-cells = <0x0>;
118 #power-domain-cells = <0x0>;
123 /* fixme: what to attach to */
124 #power-domain-cells = <0x0>;
129 #power-domain-cells = <0x0>;
134 #power-domain-cells = <0x0>;
139 #power-domain-cells = <0x0>;
144 #power-domain-cells = <0x0>;
149 #power-domain-cells = <0x0>;
154 #power-domain-cells = <0x0>;
159 #power-domain-cells = <0x0>;
164 #power-domain-cells = <0x0>;
169 #power-domain-cells = <0x0>;
174 #power-domain-cells = <0x0>;
179 #power-domain-cells = <0x0>;
184 #power-domain-cells = <0x0>;
189 #power-domain-cells = <0x0>;
194 #power-domain-cells = <0x0>;
199 #power-domain-cells = <0x0>;
200 pd-id = <0x3a 0x14 0x15>;
205 compatible = "arm,armv8-pmuv3";
206 interrupt-parent = <&gic>;
207 interrupts = <0 143 4>,
214 compatible = "arm,psci-0.2";
219 compatible = "xlnx,zynqmp-pm";
224 compatible = "arm,armv8-timer";
225 interrupt-parent = <&gic>;
226 interrupts = <1 13 0xf01>,
233 compatible = "arm,cortex-a53-edac";
237 compatible = "xlnx,zynqmp-pcap-fpga";
240 amba_apu: amba_apu@0 {
241 compatible = "simple-bus";
242 #address-cells = <2>;
244 ranges = <0 0 0 0 0xffffffff>;
246 gic: interrupt-controller@f9010000 {
247 compatible = "arm,gic-400", "arm,cortex-a15-gic";
248 #interrupt-cells = <3>;
249 reg = <0x0 0xf9010000 0x10000>,
250 <0x0 0xf9020000 0x20000>,
251 <0x0 0xf9040000 0x20000>,
252 <0x0 0xf9060000 0x20000>;
253 interrupt-controller;
254 interrupt-parent = <&gic>;
255 interrupts = <1 9 0xf04>;
260 compatible = "simple-bus";
262 #address-cells = <2>;
264 ranges = <0 0 0 0 0xffffffff>;
267 compatible = "xlnx,zynq-can-1.0";
269 clock-names = "can_clk", "pclk";
270 reg = <0x0 0xff060000 0x1000>;
271 interrupts = <0 23 4>;
272 interrupt-parent = <&gic>;
273 tx-fifo-depth = <0x40>;
274 rx-fifo-depth = <0x40>;
275 power-domains = <&pd_can0>;
279 compatible = "xlnx,zynq-can-1.0";
281 clock-names = "can_clk", "pclk";
282 reg = <0x0 0xff070000 0x1000>;
283 interrupts = <0 24 4>;
284 interrupt-parent = <&gic>;
285 tx-fifo-depth = <0x40>;
286 rx-fifo-depth = <0x40>;
287 power-domains = <&pd_can1>;
291 compatible = "arm,cci-400";
292 reg = <0x0 0xfd6e0000 0x9000>;
293 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
294 #address-cells = <1>;
298 compatible = "arm,cci-400-pmu,r1";
299 reg = <0x9000 0x5000>;
300 interrupt-parent = <&gic>;
301 interrupts = <0 123 4>,
310 fpd_dma_chan1: dma@fd500000 {
312 compatible = "xlnx,zynqmp-dma-1.0";
313 reg = <0x0 0xfd500000 0x1000>;
314 interrupt-parent = <&gic>;
315 interrupts = <0 124 4>;
316 clock-names = "clk_main", "clk_apb";
317 xlnx,bus-width = <128>;
318 #stream-id-cells = <1>;
319 iommus = <&smmu 0x14e8>;
320 power-domains = <&pd_gdma>;
323 fpd_dma_chan2: dma@fd510000 {
325 compatible = "xlnx,zynqmp-dma-1.0";
326 reg = <0x0 0xfd510000 0x1000>;
327 interrupt-parent = <&gic>;
328 interrupts = <0 125 4>;
329 clock-names = "clk_main", "clk_apb";
330 xlnx,bus-width = <128>;
331 #stream-id-cells = <1>;
332 iommus = <&smmu 0x14e9>;
333 power-domains = <&pd_gdma>;
336 fpd_dma_chan3: dma@fd520000 {
338 compatible = "xlnx,zynqmp-dma-1.0";
339 reg = <0x0 0xfd520000 0x1000>;
340 interrupt-parent = <&gic>;
341 interrupts = <0 126 4>;
342 clock-names = "clk_main", "clk_apb";
343 xlnx,bus-width = <128>;
344 #stream-id-cells = <1>;
345 iommus = <&smmu 0x14ea>;
346 power-domains = <&pd_gdma>;
349 fpd_dma_chan4: dma@fd530000 {
351 compatible = "xlnx,zynqmp-dma-1.0";
352 reg = <0x0 0xfd530000 0x1000>;
353 interrupt-parent = <&gic>;
354 interrupts = <0 127 4>;
355 clock-names = "clk_main", "clk_apb";
356 xlnx,bus-width = <128>;
357 #stream-id-cells = <1>;
358 iommus = <&smmu 0x14eb>;
359 power-domains = <&pd_gdma>;
362 fpd_dma_chan5: dma@fd540000 {
364 compatible = "xlnx,zynqmp-dma-1.0";
365 reg = <0x0 0xfd540000 0x1000>;
366 interrupt-parent = <&gic>;
367 interrupts = <0 128 4>;
368 clock-names = "clk_main", "clk_apb";
369 xlnx,bus-width = <128>;
370 #stream-id-cells = <1>;
371 iommus = <&smmu 0x14ec>;
372 power-domains = <&pd_gdma>;
375 fpd_dma_chan6: dma@fd550000 {
377 compatible = "xlnx,zynqmp-dma-1.0";
378 reg = <0x0 0xfd550000 0x1000>;
379 interrupt-parent = <&gic>;
380 interrupts = <0 129 4>;
381 clock-names = "clk_main", "clk_apb";
382 xlnx,bus-width = <128>;
383 #stream-id-cells = <1>;
384 iommus = <&smmu 0x14ed>;
385 power-domains = <&pd_gdma>;
388 fpd_dma_chan7: dma@fd560000 {
390 compatible = "xlnx,zynqmp-dma-1.0";
391 reg = <0x0 0xfd560000 0x1000>;
392 interrupt-parent = <&gic>;
393 interrupts = <0 130 4>;
394 clock-names = "clk_main", "clk_apb";
395 xlnx,bus-width = <128>;
396 #stream-id-cells = <1>;
397 iommus = <&smmu 0x14ee>;
398 power-domains = <&pd_gdma>;
401 fpd_dma_chan8: dma@fd570000 {
403 compatible = "xlnx,zynqmp-dma-1.0";
404 reg = <0x0 0xfd570000 0x1000>;
405 interrupt-parent = <&gic>;
406 interrupts = <0 131 4>;
407 clock-names = "clk_main", "clk_apb";
408 xlnx,bus-width = <128>;
409 #stream-id-cells = <1>;
410 iommus = <&smmu 0x14ef>;
411 power-domains = <&pd_gdma>;
416 compatible = "arm,mali-400", "arm,mali-utgard";
417 reg = <0x0 0xfd4b0000 0x30000>;
418 interrupt-parent = <&gic>;
419 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
420 interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
421 power-domains = <&pd_gpu>;
425 lpd_dma_chan1: dma@ffa80000 {
427 compatible = "xlnx,zynqmp-dma-1.0";
428 reg = <0x0 0xffa80000 0x1000>;
429 interrupt-parent = <&gic>;
430 interrupts = <0 77 4>;
431 xlnx,bus-width = <64>;
432 #stream-id-cells = <1>;
433 iommus = <&smmu 0x868>;
434 power-domains = <&pd_adma>;
437 lpd_dma_chan2: dma@ffa90000 {
439 compatible = "xlnx,zynqmp-dma-1.0";
440 reg = <0x0 0xffa90000 0x1000>;
441 interrupt-parent = <&gic>;
442 interrupts = <0 78 4>;
443 xlnx,bus-width = <64>;
444 #stream-id-cells = <1>;
445 iommus = <&smmu 0x869>;
446 power-domains = <&pd_adma>;
449 lpd_dma_chan3: dma@ffaa0000 {
451 compatible = "xlnx,zynqmp-dma-1.0";
452 reg = <0x0 0xffaa0000 0x1000>;
453 interrupt-parent = <&gic>;
454 interrupts = <0 79 4>;
455 xlnx,bus-width = <64>;
456 #stream-id-cells = <1>;
457 iommus = <&smmu 0x86a>;
458 power-domains = <&pd_adma>;
461 lpd_dma_chan4: dma@ffab0000 {
463 compatible = "xlnx,zynqmp-dma-1.0";
464 reg = <0x0 0xffab0000 0x1000>;
465 interrupt-parent = <&gic>;
466 interrupts = <0 80 4>;
467 xlnx,bus-width = <64>;
468 #stream-id-cells = <1>;
469 iommus = <&smmu 0x86b>;
470 power-domains = <&pd_adma>;
473 lpd_dma_chan5: dma@ffac0000 {
475 compatible = "xlnx,zynqmp-dma-1.0";
476 reg = <0x0 0xffac0000 0x1000>;
477 interrupt-parent = <&gic>;
478 interrupts = <0 81 4>;
479 xlnx,bus-width = <64>;
480 #stream-id-cells = <1>;
481 iommus = <&smmu 0x86c>;
482 power-domains = <&pd_adma>;
485 lpd_dma_chan6: dma@ffad0000 {
487 compatible = "xlnx,zynqmp-dma-1.0";
488 reg = <0x0 0xffad0000 0x1000>;
489 interrupt-parent = <&gic>;
490 interrupts = <0 82 4>;
491 xlnx,bus-width = <64>;
492 #stream-id-cells = <1>;
493 iommus = <&smmu 0x86d>;
494 power-domains = <&pd_adma>;
497 lpd_dma_chan7: dma@ffae0000 {
499 compatible = "xlnx,zynqmp-dma-1.0";
500 reg = <0x0 0xffae0000 0x1000>;
501 interrupt-parent = <&gic>;
502 interrupts = <0 83 4>;
503 xlnx,bus-width = <64>;
504 #stream-id-cells = <1>;
505 iommus = <&smmu 0x86e>;
506 power-domains = <&pd_adma>;
509 lpd_dma_chan8: dma@ffaf0000 {
511 compatible = "xlnx,zynqmp-dma-1.0";
512 reg = <0x0 0xffaf0000 0x1000>;
513 interrupt-parent = <&gic>;
514 interrupts = <0 84 4>;
515 xlnx,bus-width = <64>;
516 #stream-id-cells = <1>;
517 iommus = <&smmu 0x86f>;
518 power-domains = <&pd_adma>;
521 mc: memory-controller@fd070000 {
522 compatible = "xlnx,zynqmp-ddrc-2.40a";
523 reg = <0x0 0xfd070000 0x30000>;
524 interrupt-parent = <&gic>;
525 interrupts = <0 112 4>;
528 nand0: nand@ff100000 {
529 compatible = "arasan,nfc-v3p10";
531 reg = <0x0 0xff100000 0x1000>;
532 clock-names = "clk_sys", "clk_flash";
533 interrupt-parent = <&gic>;
534 interrupts = <0 14 4>;
535 #address-cells = <2>;
537 #stream-id-cells = <1>;
538 iommus = <&smmu 0x872>;
539 power-domains = <&pd_nand>;
542 gem0: ethernet@ff0b0000 {
543 compatible = "cdns,zynqmp-gem";
545 interrupt-parent = <&gic>;
546 interrupts = <0 57 4>, <0 57 4>;
547 reg = <0x0 0xff0b0000 0x1000>;
548 clock-names = "pclk", "hclk", "tx_clk";
549 #address-cells = <1>;
551 #stream-id-cells = <1>;
552 iommus = <&smmu 0x874>;
553 power-domains = <&pd_eth0>;
556 gem1: ethernet@ff0c0000 {
557 compatible = "cdns,zynqmp-gem";
559 interrupt-parent = <&gic>;
560 interrupts = <0 59 4>, <0 59 4>;
561 reg = <0x0 0xff0c0000 0x1000>;
562 clock-names = "pclk", "hclk", "tx_clk";
563 #address-cells = <1>;
565 #stream-id-cells = <1>;
566 iommus = <&smmu 0x875>;
567 power-domains = <&pd_eth1>;
570 gem2: ethernet@ff0d0000 {
571 compatible = "cdns,zynqmp-gem";
573 interrupt-parent = <&gic>;
574 interrupts = <0 61 4>, <0 61 4>;
575 reg = <0x0 0xff0d0000 0x1000>;
576 clock-names = "pclk", "hclk", "tx_clk";
577 #address-cells = <1>;
579 #stream-id-cells = <1>;
580 iommus = <&smmu 0x876>;
581 power-domains = <&pd_eth2>;
584 gem3: ethernet@ff0e0000 {
585 compatible = "cdns,zynqmp-gem";
587 interrupt-parent = <&gic>;
588 interrupts = <0 63 4>, <0 63 4>;
589 reg = <0x0 0xff0e0000 0x1000>;
590 clock-names = "pclk", "hclk", "tx_clk";
591 #address-cells = <1>;
593 #stream-id-cells = <1>;
594 iommus = <&smmu 0x877>;
595 power-domains = <&pd_eth3>;
598 gpio: gpio@ff0a0000 {
599 compatible = "xlnx,zynqmp-gpio-1.0";
602 interrupt-parent = <&gic>;
603 interrupts = <0 16 4>;
604 interrupt-controller;
605 #interrupt-cells = <2>;
606 reg = <0x0 0xff0a0000 0x1000>;
607 power-domains = <&pd_gpio>;
611 compatible = "cdns,i2c-r1p10";
613 interrupt-parent = <&gic>;
614 interrupts = <0 17 4>;
615 reg = <0x0 0xff020000 0x1000>;
616 #address-cells = <1>;
618 power-domains = <&pd_i2c0>;
622 compatible = "cdns,i2c-r1p10";
624 interrupt-parent = <&gic>;
625 interrupts = <0 18 4>;
626 reg = <0x0 0xff030000 0x1000>;
627 #address-cells = <1>;
629 power-domains = <&pd_i2c1>;
632 ocm: memory-controller@ff960000 {
633 compatible = "xlnx,zynqmp-ocmc-1.0";
634 reg = <0x0 0xff960000 0x1000>;
635 interrupt-parent = <&gic>;
636 interrupts = <0 10 4>;
639 pcie: pcie@fd0e0000 {
640 compatible = "xlnx,nwl-pcie-2.11";
642 #address-cells = <3>;
644 #interrupt-cells = <1>;
647 interrupt-parent = <&gic>;
648 interrupts = <0 118 4>,
651 <0 115 4>, /* MSI_1 [63...32] */
652 <0 114 4>; /* MSI_0 [31...0] */
653 interrupt-names = "misc","dummy","intx", "msi1", "msi0";
654 msi-parent = <&pcie>;
655 reg = <0x0 0xfd0e0000 0x1000>,
656 <0x0 0xfd480000 0x1000>,
657 <0x0 0xe0000000 0x1000000>;
658 reg-names = "breg", "pcireg", "cfg";
659 ranges = <0x02000000 0x00000000 0xe1000000 0x00000000 0xe1000000 0 0x0f000000>;
660 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
661 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
662 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
663 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
664 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
665 power-domains = <&pd_pcie>;
666 pcie_intc: legacy-interrupt-controller {
667 interrupt-controller;
668 #address-cells = <0>;
669 #interrupt-cells = <1>;
674 compatible = "xlnx,zynqmp-qspi-1.0";
676 clock-names = "ref_clk", "pclk";
677 interrupts = <0 15 4>;
678 interrupt-parent = <&gic>;
680 reg = <0x0 0xff0f0000 0x1000>,
681 <0x0 0xc0000000 0x8000000>;
682 #address-cells = <1>;
684 #stream-id-cells = <1>;
685 iommus = <&smmu 0x873>;
686 power-domains = <&pd_qspi>;
690 compatible = "xlnx,zynqmp-rtc";
692 reg = <0x0 0xffa60000 0x100>;
693 interrupt-parent = <&gic>;
694 interrupts = <0 26 4>, <0 27 4>;
695 interrupt-names = "alarm", "sec";
698 serdes: zynqmp_phy@fd400000 {
699 compatible = "xlnx,zynqmp-psgtr";
701 reg = <0x0 0xfd400000 0x40000>,
702 <0x0 0xfd3d0000 0x1000>,
703 <0x0 0xfd1a0000 0x1000>,
704 <0x0 0xff5e0000 0x1000>;
705 reg-names = "serdes", "siou", "fpd", "lpd";
706 xlnx,tx_termination_fix;
721 sata: ahci@fd0c0000 {
722 compatible = "ceva,ahci-1v84";
724 reg = <0x0 0xfd0c0000 0x2000>;
725 interrupt-parent = <&gic>;
726 interrupts = <0 133 4>;
727 power-domains = <&pd_sata>;
730 sdhci0: sdhci@ff160000 {
732 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
734 interrupt-parent = <&gic>;
735 interrupts = <0 48 4>;
736 reg = <0x0 0xff160000 0x1000>;
737 clock-names = "clk_xin", "clk_ahb";
738 xlnx,device_id = <0>;
739 #stream-id-cells = <1>;
740 iommus = <&smmu 0x870>;
741 power-domains = <&pd_sd0>;
744 sdhci1: sdhci@ff170000 {
746 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
748 interrupt-parent = <&gic>;
749 interrupts = <0 49 4>;
750 reg = <0x0 0xff170000 0x1000>;
751 clock-names = "clk_xin", "clk_ahb";
752 xlnx,device_id = <1>;
753 #stream-id-cells = <1>;
754 iommus = <&smmu 0x871>;
755 power-domains = <&pd_sd1>;
758 smmu: smmu@fd800000 {
759 compatible = "arm,mmu-500";
760 reg = <0x0 0xfd800000 0x20000>;
762 #global-interrupts = <1>;
763 interrupt-parent = <&gic>;
764 interrupts = <0 155 4>,
765 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
766 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
767 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
768 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
769 mmu-masters = < &gem0 0x874
784 &fpd_dma_chan1 0x14e8
785 &fpd_dma_chan2 0x14e9
786 &fpd_dma_chan3 0x14ea
787 &fpd_dma_chan4 0x14eb
788 &fpd_dma_chan5 0x14ec
789 &fpd_dma_chan6 0x14ed
790 &fpd_dma_chan7 0x14ee
791 &fpd_dma_chan8 0x14ef
798 compatible = "cdns,spi-r1p6";
800 interrupt-parent = <&gic>;
801 interrupts = <0 19 4>;
802 reg = <0x0 0xff040000 0x1000>;
803 clock-names = "ref_clk", "pclk";
804 #address-cells = <1>;
806 power-domains = <&pd_spi0>;
810 compatible = "cdns,spi-r1p6";
812 interrupt-parent = <&gic>;
813 interrupts = <0 20 4>;
814 reg = <0x0 0xff050000 0x1000>;
815 clock-names = "ref_clk", "pclk";
816 #address-cells = <1>;
818 power-domains = <&pd_spi1>;
821 ttc0: timer@ff110000 {
822 compatible = "cdns,ttc";
824 interrupt-parent = <&gic>;
825 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
826 reg = <0x0 0xff110000 0x1000>;
828 power-domains = <&pd_ttc0>;
831 ttc1: timer@ff120000 {
832 compatible = "cdns,ttc";
834 interrupt-parent = <&gic>;
835 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
836 reg = <0x0 0xff120000 0x1000>;
838 power-domains = <&pd_ttc1>;
841 ttc2: timer@ff130000 {
842 compatible = "cdns,ttc";
844 interrupt-parent = <&gic>;
845 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
846 reg = <0x0 0xff130000 0x1000>;
848 power-domains = <&pd_ttc2>;
851 ttc3: timer@ff140000 {
852 compatible = "cdns,ttc";
854 interrupt-parent = <&gic>;
855 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
856 reg = <0x0 0xff140000 0x1000>;
858 power-domains = <&pd_ttc3>;
861 uart0: serial@ff000000 {
863 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
865 interrupt-parent = <&gic>;
866 interrupts = <0 21 4>;
867 reg = <0x0 0xff000000 0x1000>;
868 clock-names = "uart_clk", "pclk";
869 power-domains = <&pd_uart0>;
872 uart1: serial@ff010000 {
874 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
876 interrupt-parent = <&gic>;
877 interrupts = <0 22 4>;
878 reg = <0x0 0xff010000 0x1000>;
879 clock-names = "uart_clk", "pclk";
880 power-domains = <&pd_uart1>;
884 #address-cells = <2>;
887 compatible = "xlnx,zynqmp-dwc3";
888 clock-names = "bus_clk", "ref_clk";
889 clocks = <&clk125>, <&clk125>;
890 #stream-id-cells = <1>;
891 iommus = <&smmu 0x860>;
892 power-domains = <&pd_usb0>;
895 dwc3_0: dwc3@fe200000 {
896 compatible = "snps,dwc3";
898 reg = <0x0 0xfe200000 0x40000>;
899 interrupt-parent = <&gic>;
900 interrupts = <0 65 4>;
901 /* snps,quirk-frame-length-adjustment = <0x20>; */
907 #address-cells = <2>;
910 compatible = "xlnx,zynqmp-dwc3";
911 clock-names = "bus_clk", "ref_clk";
912 clocks = <&clk125>, <&clk125>;
913 #stream-id-cells = <1>;
914 iommus = <&smmu 0x861>;
915 power-domains = <&pd_usb1>;
918 dwc3_1: dwc3@fe300000 {
919 compatible = "snps,dwc3";
921 reg = <0x0 0xfe300000 0x40000>;
922 interrupt-parent = <&gic>;
923 interrupts = <0 70 4>;
924 /* snps,quirk-frame-length-adjustment = <0x20>; */
929 watchdog0: watchdog@fd4d0000 {
930 compatible = "cdns,wdt-r1p2";
932 interrupt-parent = <&gic>;
933 interrupts = <0 113 1>;
934 reg = <0x0 0xfd4d0000 0x1000>;
938 xilinx_drm: xilinx_drm {
939 compatible = "xlnx,drm";
941 xlnx,encoder-slave = <&xlnx_dp>;
942 xlnx,connector-type = "DisplayPort";
943 xlnx,dp-sub = <&xlnx_dp_sub>;
945 xlnx,pixel-format = "rgb565";
947 dmas = <&xlnx_dpdma 3>;
951 dmas = <&xlnx_dpdma 0>,
954 dma-names = "dma0", "dma1", "dma2";
959 xlnx_dp: dp@fd4a0000 {
960 compatible = "xlnx,v-dp";
962 reg = <0x0 0xfd4a0000 0x1000>;
963 interrupts = <0 119 4>;
964 interrupt-parent = <&gic>;
965 clock-names = "aclk", "aud_clk";
966 xlnx,dp-version = "v1.2";
967 xlnx,max-lanes = <2>;
968 xlnx,max-link-rate = <540000>;
971 xlnx,colormetry = "rgb";
973 xlnx,audio-chan = <2>;
974 xlnx,dp-sub = <&xlnx_dp_sub>;
975 xlnx,max-pclock-frequency = <300000>;
978 xlnx_dp_snd_card: dp_snd_card {
979 compatible = "xlnx,dp-snd-card";
981 xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
982 xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
985 xlnx_dp_snd_codec0: dp_snd_codec0 {
986 compatible = "xlnx,dp-snd-codec";
988 clock-names = "aud_clk";
991 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
992 compatible = "xlnx,dp-snd-pcm";
994 dmas = <&xlnx_dpdma 4>;
998 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
999 compatible = "xlnx,dp-snd-pcm";
1000 status = "disabled";
1001 dmas = <&xlnx_dpdma 5>;
1005 xlnx_dp_sub: dp_sub@fd4aa000 {
1006 compatible = "xlnx,dp-sub";
1007 status = "disabled";
1008 reg = <0x0 0xfd4aa000 0x1000>,
1009 <0x0 0xfd4ab000 0x1000>,
1010 <0x0 0xfd4ac000 0x1000>;
1011 reg-names = "blend", "av_buf", "aud";
1012 xlnx,output-fmt = "rgb";
1013 xlnx,vid-fmt = "yuyv";
1014 xlnx,gfx-fmt = "rgb565";
1017 xlnx_dpdma: dma@fd4c0000 {
1018 compatible = "xlnx,dpdma";
1019 status = "disabled";
1020 reg = <0x0 0xfd4c0000 0x1000>;
1021 interrupts = <0 122 4>;
1022 interrupt-parent = <&gic>;
1023 clock-names = "axi_clk";
1027 compatible = "xlnx,video0";
1030 compatible = "xlnx,video1";
1033 compatible = "xlnx,video2";
1035 dma-graphicschannel {
1036 compatible = "xlnx,graphics";
1039 compatible = "xlnx,audio0";
1042 compatible = "xlnx,audio1";