git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynqmp.dtsi

   1 /*
   2  * dts file for Xilinx ZynqMP
   3  *
   4  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 / {
  12         compatible = "xlnx,zynqmp";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu0: cpu@0 {
  21                         compatible = "arm,cortex-a53", "arm,armv8";
  22                         device_type = "cpu";
  23                         enable-method = "psci";
  24                         operating-points-v2 = <&cpu_opp_table>;
  25                         reg = <0x0>;
  26                         cpu-idle-states = <&CPU_SLEEP_0>;
  27                 };
  28
  29                 cpu1: cpu@1 {
  30                         compatible = "arm,cortex-a53", "arm,armv8";
  31                         device_type = "cpu";
  32                         enable-method = "psci";
  33                         reg = <0x1>;
  34                         operating-points-v2 = <&cpu_opp_table>;
  35                         cpu-idle-states = <&CPU_SLEEP_0>;
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         compatible = "arm,cortex-a53", "arm,armv8";
  40                         device_type = "cpu";
  41                         enable-method = "psci";
  42                         reg = <0x2>;
  43                         operating-points-v2 = <&cpu_opp_table>;
  44                         cpu-idle-states = <&CPU_SLEEP_0>;
  45                 };
  46
  47                 cpu3: cpu@3 {
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         device_type = "cpu";
  50                         enable-method = "psci";
  51                         reg = <0x3>;
  52                         operating-points-v2 = <&cpu_opp_table>;
  53                         cpu-idle-states = <&CPU_SLEEP_0>;
  54                 };
  55
  56                 idle-states {
  57                         entry-method = "arm,psci";
  58
  59                         CPU_SLEEP_0: cpu-sleep-0 {
  60                                 compatible = "arm,idle-state";
  61                                 arm,psci-suspend-param = <0x40000000>;
  62                                 local-timer-stop;
  63                                 entry-latency-us = <300>;
  64                                 exit-latency-us = <600>;
  65                                 min-residency-us = <10000>;
  66                         };
  67                 };
  68         };
  69
  70         cpu_opp_table: cpu_opp_table {
  71                 compatible = "operating-points-v2";
  72                 opp-shared;
  73                 opp00 {
  74                         opp-hz = /bits/ 64 <1199999988>;
  75                         opp-microvolt = <1000000>;
  76                         clock-latency-ns = <500000>;
  77                 };
  78                 opp01 {
  79                         opp-hz = /bits/ 64 <599999994>;
  80                         opp-microvolt = <1000000>;
  81                         clock-latency-ns = <500000>;
  82                 };
  83                 opp02 {
  84                         opp-hz = /bits/ 64 <399999996>;
  85                         opp-microvolt = <1000000>;
  86                         clock-latency-ns = <500000>;
  87                 };
  88                 opp03 {
  89                         opp-hz = /bits/ 64 <299999997>;
  90                         opp-microvolt = <1000000>;
  91                         clock-latency-ns = <500000>;
  92                 };
  93         };
  94
  95         dcc: dcc {
  96                 compatible = "arm,dcc";
  97                 status = "disabled";
  98                 u-boot,dm-pre-reloc;
  99         };
 100
 101         power-domains {
 102                 compatible = "xlnx,zynqmp-genpd";
 103
 104                 pd_usb0: pd-usb0 {
 105                         #power-domain-cells = <0x0>;
 106                         pd-id = <0x16>;
 107                 };
 108
 109                 pd_usb1: pd-usb1 {
 110                         #power-domain-cells = <0x0>;
 111                         pd-id = <0x17>;
 112                 };
 113
 114                 pd_sata: pd-sata {
 115                         #power-domain-cells = <0x0>;
 116                         pd-id = <0x1c>;
 117                 };
 118
 119                 pd_spi0: pd-spi0 {
 120                         #power-domain-cells = <0x0>;
 121                         pd-id = <0x23>;
 122                 };
 123
 124                 pd_spi1: pd-spi1 {
 125                         #power-domain-cells = <0x0>;
 126                         pd-id = <0x24>;
 127                 };
 128
 129                 pd_uart0: pd-uart0 {
 130                         #power-domain-cells = <0x0>;
 131                         pd-id = <0x21>;
 132                 };
 133
 134                 pd_uart1: pd-uart1 {
 135                         #power-domain-cells = <0x0>;
 136                         pd-id = <0x22>;
 137                 };
 138
 139                 pd_eth0: pd-eth0 {
 140                         #power-domain-cells = <0x0>;
 141                         pd-id = <0x1d>;
 142                 };
 143
 144                 pd_eth1: pd-eth1 {
 145                         #power-domain-cells = <0x0>;
 146                         pd-id = <0x1e>;
 147                 };
 148
 149                 pd_eth2: pd-eth2 {
 150                         #power-domain-cells = <0x0>;
 151                         pd-id = <0x1f>;
 152                 };
 153
 154                 pd_eth3: pd-eth3 {
 155                         #power-domain-cells = <0x0>;
 156                         pd-id = <0x20>;
 157                 };
 158
 159                 pd_i2c0: pd-i2c0 {
 160                         #power-domain-cells = <0x0>;
 161                         pd-id = <0x25>;
 162                 };
 163
 164                 pd_i2c1: pd-i2c1 {
 165                         #power-domain-cells = <0x0>;
 166                         pd-id = <0x26>;
 167                 };
 168
 169                 pd_dp: pd-dp {
 170                         #power-domain-cells = <0x0>;
 171                         pd-id = <0x29>;
 172                 };
 173
 174                 pd_gdma: pd-gdma {
 175                         #power-domain-cells = <0x0>;
 176                         pd-id = <0x2a>;
 177                 };
 178
 179                 pd_adma: pd-adma {
 180                         #power-domain-cells = <0x0>;
 181                         pd-id = <0x2b>;
 182                 };
 183
 184                 pd_ttc0: pd-ttc0 {
 185                         #power-domain-cells = <0x0>;
 186                         pd-id = <0x18>;
 187                 };
 188
 189                 pd_ttc1: pd-ttc1 {
 190                         #power-domain-cells = <0x0>;
 191                         pd-id = <0x19>;
 192                 };
 193
 194                 pd_ttc2: pd-ttc2 {
 195                         #power-domain-cells = <0x0>;
 196                         pd-id = <0x1a>;
 197                 };
 198
 199                 pd_ttc3: pd-ttc3 {
 200                         #power-domain-cells = <0x0>;
 201                         pd-id = <0x1b>;
 202                 };
 203
 204                 pd_sd0: pd-sd0 {
 205                         #power-domain-cells = <0x0>;
 206                         pd-id = <0x27>;
 207                 };
 208
 209                 pd_sd1: pd-sd1 {
 210                         #power-domain-cells = <0x0>;
 211                         pd-id = <0x28>;
 212                 };
 213
 214                 pd_nand: pd-nand {
 215                         #power-domain-cells = <0x0>;
 216                         pd-id = <0x2c>;
 217                 };
 218
 219                 pd_qspi: pd-qspi {
 220                         #power-domain-cells = <0x0>;
 221                         pd-id = <0x2d>;
 222                 };
 223
 224                 pd_gpio: pd-gpio {
 225                         #power-domain-cells = <0x0>;
 226                         pd-id = <0x2e>;
 227                 };
 228
 229                 pd_can0: pd-can0 {
 230                         #power-domain-cells = <0x0>;
 231                         pd-id = <0x2f>;
 232                 };
 233
 234                 pd_can1: pd-can1 {
 235                         #power-domain-cells = <0x0>;
 236                         pd-id = <0x30>;
 237                 };
 238
 239                 pd_pcie: pd-pcie {
 240                         #power-domain-cells = <0x0>;
 241                         pd-id = <0x3b>;
 242                 };
 243
 244                 pd_gpu: pd-gpu {
 245                         #power-domain-cells = <0x0>;
 246                         pd-id = <0x3a 0x14 0x15>;
 247                 };
 248         };
 249
 250         pmu {
 251                 compatible = "arm,armv8-pmuv3";
 252                 interrupt-parent = <&gic>;
 253                 interrupts = <0 143 4>,
 254                              <0 144 4>,
 255                              <0 145 4>,
 256                              <0 146 4>;
 257         };
 258
 259         psci {
 260                 compatible = "arm,psci-0.2";
 261                 method = "smc";
 262         };
 263
 264         firmware {
 265                 compatible = "xlnx,zynqmp-pm";
 266                 method = "smc";
 267                 interrupt-parent = <&gic>;
 268                 interrupts = <0 35 4>;
 269         };
 270
 271         timer {
 272                 compatible = "arm,armv8-timer";
 273                 interrupt-parent = <&gic>;
 274                 interrupts = <1 13 0xf08>,
 275                              <1 14 0xf08>,
 276                              <1 11 0xf08>,
 277                              <1 10 0xf08>;
 278         };
 279
 280         edac {
 281                 compatible = "arm,cortex-a53-edac";
 282         };
 283
 284         fpga_full: fpga-full {
 285                 compatible = "fpga-region";
 286                 fpga-mgr = <&pcap>;
 287                 #address-cells = <2>;
 288                 #size-cells = <2>;
 289         };
 290
 291         nvmem_firmware {
 292                 compatible = "xlnx,zynqmp-nvmem-fw";
 293                 #address-cells = <1>;
 294                 #size-cells = <1>;
 295
 296                 soc_revision: soc_revision@0 {
 297                         reg = <0x0 0x4>;
 298                 };
 299         };
 300
 301         pcap: pcap {
 302                 compatible = "xlnx,zynqmp-pcap-fpga";
 303         };
 304
 305         rst: reset-controller {
 306                 compatible = "xlnx,zynqmp-reset";
 307                 #reset-cells = <1>;
 308         };
 309
 310         amba_apu: amba_apu@0 {
 311                 compatible = "simple-bus";
 312                 #address-cells = <2>;
 313                 #size-cells = <1>;
 314                 ranges = <0 0 0 0 0xffffffff>;
 315
 316                 gic: interrupt-controller@f9010000 {
 317                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
 318                         #interrupt-cells = <3>;
 319                         reg = <0x0 0xf9010000 0x10000>,
 320                               <0x0 0xf9020000 0x20000>,
 321                               <0x0 0xf9040000 0x20000>,
 322                               <0x0 0xf9060000 0x20000>;
 323                         interrupt-controller;
 324                         interrupt-parent = <&gic>;
 325                         interrupts = <1 9 0xf04>;
 326                 };
 327         };
 328
 329         amba: amba {
 330                 compatible = "simple-bus";
 331                 u-boot,dm-pre-reloc;
 332                 #address-cells = <2>;
 333                 #size-cells = <2>;
 334                 ranges;
 335
 336                 can0: can@ff060000 {
 337                         compatible = "xlnx,zynq-can-1.0";
 338                         status = "disabled";
 339                         clock-names = "can_clk", "pclk";
 340                         reg = <0x0 0xff060000 0x0 0x1000>;
 341                         interrupts = <0 23 4>;
 342                         interrupt-parent = <&gic>;
 343                         tx-fifo-depth = <0x40>;
 344                         rx-fifo-depth = <0x40>;
 345                         power-domains = <&pd_can0>;
 346                 };
 347
 348                 can1: can@ff070000 {
 349                         compatible = "xlnx,zynq-can-1.0";
 350                         status = "disabled";
 351                         clock-names = "can_clk", "pclk";
 352                         reg = <0x0 0xff070000 0x0 0x1000>;
 353                         interrupts = <0 24 4>;
 354                         interrupt-parent = <&gic>;
 355                         tx-fifo-depth = <0x40>;
 356                         rx-fifo-depth = <0x40>;
 357                         power-domains = <&pd_can1>;
 358                 };
 359
 360                 cci: cci@fd6e0000 {
 361                         compatible = "arm,cci-400";
 362                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 363                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 364                         #address-cells = <1>;
 365                         #size-cells = <1>;
 366
 367                         pmu@9000 {
 368                                 compatible = "arm,cci-400-pmu,r1";
 369                                 reg = <0x9000 0x5000>;
 370                                 interrupt-parent = <&gic>;
 371                                 interrupts = <0 123 4>,
 372                                              <0 123 4>,
 373                                              <0 123 4>,
 374                                              <0 123 4>,
 375                                              <0 123 4>;
 376                         };
 377                 };
 378
 379                 /* GDMA */
 380                 fpd_dma_chan1: dma@fd500000 {
 381                         status = "disabled";
 382                         compatible = "xlnx,zynqmp-dma-1.0";
 383                         reg = <0x0 0xfd500000 0x0 0x1000>;
 384                         interrupt-parent = <&gic>;
 385                         interrupts = <0 124 4>;
 386                         clock-names = "clk_main", "clk_apb";
 387                         xlnx,bus-width = <128>;
 388                         #stream-id-cells = <1>;
 389                         iommus = <&smmu 0x14e8>;
 390                         power-domains = <&pd_gdma>;
 391                 };
 392
 393                 fpd_dma_chan2: dma@fd510000 {
 394                         status = "disabled";
 395                         compatible = "xlnx,zynqmp-dma-1.0";
 396                         reg = <0x0 0xfd510000 0x0 0x1000>;
 397                         interrupt-parent = <&gic>;
 398                         interrupts = <0 125 4>;
 399                         clock-names = "clk_main", "clk_apb";
 400                         xlnx,bus-width = <128>;
 401                         #stream-id-cells = <1>;
 402                         iommus = <&smmu 0x14e9>;
 403                         power-domains = <&pd_gdma>;
 404                 };
 405
 406                 fpd_dma_chan3: dma@fd520000 {
 407                         status = "disabled";
 408                         compatible = "xlnx,zynqmp-dma-1.0";
 409                         reg = <0x0 0xfd520000 0x0 0x1000>;
 410                         interrupt-parent = <&gic>;
 411                         interrupts = <0 126 4>;
 412                         clock-names = "clk_main", "clk_apb";
 413                         xlnx,bus-width = <128>;
 414                         #stream-id-cells = <1>;
 415                         iommus = <&smmu 0x14ea>;
 416                         power-domains = <&pd_gdma>;
 417                 };
 418
 419                 fpd_dma_chan4: dma@fd530000 {
 420                         status = "disabled";
 421                         compatible = "xlnx,zynqmp-dma-1.0";
 422                         reg = <0x0 0xfd530000 0x0 0x1000>;
 423                         interrupt-parent = <&gic>;
 424                         interrupts = <0 127 4>;
 425                         clock-names = "clk_main", "clk_apb";
 426                         xlnx,bus-width = <128>;
 427                         #stream-id-cells = <1>;
 428                         iommus = <&smmu 0x14eb>;
 429                         power-domains = <&pd_gdma>;
 430                 };
 431
 432                 fpd_dma_chan5: dma@fd540000 {
 433                         status = "disabled";
 434                         compatible = "xlnx,zynqmp-dma-1.0";
 435                         reg = <0x0 0xfd540000 0x0 0x1000>;
 436                         interrupt-parent = <&gic>;
 437                         interrupts = <0 128 4>;
 438                         clock-names = "clk_main", "clk_apb";
 439                         xlnx,bus-width = <128>;
 440                         #stream-id-cells = <1>;
 441                         iommus = <&smmu 0x14ec>;
 442                         power-domains = <&pd_gdma>;
 443                 };
 444
 445                 fpd_dma_chan6: dma@fd550000 {
 446                         status = "disabled";
 447                         compatible = "xlnx,zynqmp-dma-1.0";
 448                         reg = <0x0 0xfd550000 0x0 0x1000>;
 449                         interrupt-parent = <&gic>;
 450                         interrupts = <0 129 4>;
 451                         clock-names = "clk_main", "clk_apb";
 452                         xlnx,bus-width = <128>;
 453                         #stream-id-cells = <1>;
 454                         iommus = <&smmu 0x14ed>;
 455                         power-domains = <&pd_gdma>;
 456                 };
 457
 458                 fpd_dma_chan7: dma@fd560000 {
 459                         status = "disabled";
 460                         compatible = "xlnx,zynqmp-dma-1.0";
 461                         reg = <0x0 0xfd560000 0x0 0x1000>;
 462                         interrupt-parent = <&gic>;
 463                         interrupts = <0 130 4>;
 464                         clock-names = "clk_main", "clk_apb";
 465                         xlnx,bus-width = <128>;
 466                         #stream-id-cells = <1>;
 467                         iommus = <&smmu 0x14ee>;
 468                         power-domains = <&pd_gdma>;
 469                 };
 470
 471                 fpd_dma_chan8: dma@fd570000 {
 472                         status = "disabled";
 473                         compatible = "xlnx,zynqmp-dma-1.0";
 474                         reg = <0x0 0xfd570000 0x0 0x1000>;
 475                         interrupt-parent = <&gic>;
 476                         interrupts = <0 131 4>;
 477                         clock-names = "clk_main", "clk_apb";
 478                         xlnx,bus-width = <128>;
 479                         #stream-id-cells = <1>;
 480                         iommus = <&smmu 0x14ef>;
 481                         power-domains = <&pd_gdma>;
 482                 };
 483
 484                 gpu: gpu@fd4b0000 {
 485                         status = "disabled";
 486                         compatible = "arm,mali-400", "arm,mali-utgard";
 487                         reg = <0x0 0xfd4b0000 0x0 0x10000>;
 488                         interrupt-parent = <&gic>;
 489                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 490                         interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
 491                         clock-names = "gpu", "gpu_pp0", "gpu_pp1";
 492                         power-domains = <&pd_gpu>;
 493                 };
 494
 495                 /* LPDDMA default allows only secured access. inorder to enable
 496                  * These dma channels, Users should ensure that these dma
 497                  * Channels are allowed for non secure access.
 498                  */
 499                 lpd_dma_chan1: dma@ffa80000 {
 500                         status = "disabled";
 501                         compatible = "xlnx,zynqmp-dma-1.0";
 502                         clock-names = "clk_main", "clk_apb";
 503                         reg = <0x0 0xffa80000 0x0 0x1000>;
 504                         interrupt-parent = <&gic>;
 505                         interrupts = <0 77 4>;
 506                         xlnx,bus-width = <64>;
 507                         #stream-id-cells = <1>;
 508                         iommus = <&smmu 0x868>;
 509                         power-domains = <&pd_adma>;
 510                 };
 511
 512                 lpd_dma_chan2: dma@ffa90000 {
 513                         status = "disabled";
 514                         compatible = "xlnx,zynqmp-dma-1.0";
 515                         clock-names = "clk_main", "clk_apb";
 516                         reg = <0x0 0xffa90000 0x0 0x1000>;
 517                         interrupt-parent = <&gic>;
 518                         interrupts = <0 78 4>;
 519                         xlnx,bus-width = <64>;
 520                         #stream-id-cells = <1>;
 521                         iommus = <&smmu 0x869>;
 522                         power-domains = <&pd_adma>;
 523                 };
 524
 525                 lpd_dma_chan3: dma@ffaa0000 {
 526                         status = "disabled";
 527                         compatible = "xlnx,zynqmp-dma-1.0";
 528                         clock-names = "clk_main", "clk_apb";
 529                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 530                         interrupt-parent = <&gic>;
 531                         interrupts = <0 79 4>;
 532                         xlnx,bus-width = <64>;
 533                         #stream-id-cells = <1>;
 534                         iommus = <&smmu 0x86a>;
 535                         power-domains = <&pd_adma>;
 536                 };
 537
 538                 lpd_dma_chan4: dma@ffab0000 {
 539                         status = "disabled";
 540                         compatible = "xlnx,zynqmp-dma-1.0";
 541                         clock-names = "clk_main", "clk_apb";
 542                         reg = <0x0 0xffab0000 0x0 0x1000>;
 543                         interrupt-parent = <&gic>;
 544                         interrupts = <0 80 4>;
 545                         xlnx,bus-width = <64>;
 546                         #stream-id-cells = <1>;
 547                         iommus = <&smmu 0x86b>;
 548                         power-domains = <&pd_adma>;
 549                 };
 550
 551                 lpd_dma_chan5: dma@ffac0000 {
 552                         status = "disabled";
 553                         compatible = "xlnx,zynqmp-dma-1.0";
 554                         clock-names = "clk_main", "clk_apb";
 555                         reg = <0x0 0xffac0000 0x0 0x1000>;
 556                         interrupt-parent = <&gic>;
 557                         interrupts = <0 81 4>;
 558                         xlnx,bus-width = <64>;
 559                         #stream-id-cells = <1>;
 560                         iommus = <&smmu 0x86c>;
 561                         power-domains = <&pd_adma>;
 562                 };
 563
 564                 lpd_dma_chan6: dma@ffad0000 {
 565                         status = "disabled";
 566                         compatible = "xlnx,zynqmp-dma-1.0";
 567                         clock-names = "clk_main", "clk_apb";
 568                         reg = <0x0 0xffad0000 0x0 0x1000>;
 569                         interrupt-parent = <&gic>;
 570                         interrupts = <0 82 4>;
 571                         xlnx,bus-width = <64>;
 572                         #stream-id-cells = <1>;
 573                         iommus = <&smmu 0x86d>;
 574                         power-domains = <&pd_adma>;
 575                 };
 576
 577                 lpd_dma_chan7: dma@ffae0000 {
 578                         status = "disabled";
 579                         compatible = "xlnx,zynqmp-dma-1.0";
 580                         clock-names = "clk_main", "clk_apb";
 581                         reg = <0x0 0xffae0000 0x0 0x1000>;
 582                         interrupt-parent = <&gic>;
 583                         interrupts = <0 83 4>;
 584                         xlnx,bus-width = <64>;
 585                         #stream-id-cells = <1>;
 586                         iommus = <&smmu 0x86e>;
 587                         power-domains = <&pd_adma>;
 588                 };
 589
 590                 lpd_dma_chan8: dma@ffaf0000 {
 591                         status = "disabled";
 592                         compatible = "xlnx,zynqmp-dma-1.0";
 593                         clock-names = "clk_main", "clk_apb";
 594                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 595                         interrupt-parent = <&gic>;
 596                         interrupts = <0 84 4>;
 597                         xlnx,bus-width = <64>;
 598                         #stream-id-cells = <1>;
 599                         iommus = <&smmu 0x86f>;
 600                         power-domains = <&pd_adma>;
 601                 };
 602
 603                 mc: memory-controller@fd070000 {
 604                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 605                         reg = <0x0 0xfd070000 0x0 0x30000>;
 606                         interrupt-parent = <&gic>;
 607                         interrupts = <0 112 4>;
 608                 };
 609
 610                 nand0: nand@ff100000 {
 611                         compatible = "arasan,nfc-v3p10";
 612                         status = "disabled";
 613                         reg = <0x0 0xff100000 0x0 0x1000>;
 614                         clock-names = "clk_sys", "clk_flash";
 615                         interrupt-parent = <&gic>;
 616                         interrupts = <0 14 4>;
 617                         #address-cells = <2>;
 618                         #size-cells = <1>;
 619                         #stream-id-cells = <1>;
 620                         iommus = <&smmu 0x872>;
 621                         power-domains = <&pd_nand>;
 622                 };
 623
 624                 gem0: ethernet@ff0b0000 {
 625                         compatible = "cdns,zynqmp-gem";
 626                         status = "disabled";
 627                         interrupt-parent = <&gic>;
 628                         interrupts = <0 57 4>, <0 57 4>;
 629                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 630                         clock-names = "pclk", "hclk", "tx_clk";
 631                         #address-cells = <1>;
 632                         #size-cells = <0>;
 633                         #stream-id-cells = <1>;
 634                         iommus = <&smmu 0x874>;
 635                         power-domains = <&pd_eth0>;
 636                 };
 637
 638                 gem1: ethernet@ff0c0000 {
 639                         compatible = "cdns,zynqmp-gem";
 640                         status = "disabled";
 641                         interrupt-parent = <&gic>;
 642                         interrupts = <0 59 4>, <0 59 4>;
 643                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 644                         clock-names = "pclk", "hclk", "tx_clk";
 645                         #address-cells = <1>;
 646                         #size-cells = <0>;
 647                         #stream-id-cells = <1>;
 648                         iommus = <&smmu 0x875>;
 649                         power-domains = <&pd_eth1>;
 650                 };
 651
 652                 gem2: ethernet@ff0d0000 {
 653                         compatible = "cdns,zynqmp-gem";
 654                         status = "disabled";
 655                         interrupt-parent = <&gic>;
 656                         interrupts = <0 61 4>, <0 61 4>;
 657                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 658                         clock-names = "pclk", "hclk", "tx_clk";
 659                         #address-cells = <1>;
 660                         #size-cells = <0>;
 661                         #stream-id-cells = <1>;
 662                         iommus = <&smmu 0x876>;
 663                         power-domains = <&pd_eth2>;
 664                 };
 665
 666                 gem3: ethernet@ff0e0000 {
 667                         compatible = "cdns,zynqmp-gem";
 668                         status = "disabled";
 669                         interrupt-parent = <&gic>;
 670                         interrupts = <0 63 4>, <0 63 4>;
 671                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 672                         clock-names = "pclk", "hclk", "tx_clk";
 673                         #address-cells = <1>;
 674                         #size-cells = <0>;
 675                         #stream-id-cells = <1>;
 676                         iommus = <&smmu 0x877>;
 677                         power-domains = <&pd_eth3>;
 678                 };
 679
 680                 gpio: gpio@ff0a0000 {
 681                         compatible = "xlnx,zynqmp-gpio-1.0";
 682                         status = "disabled";
 683                         #gpio-cells = <0x2>;
 684                         interrupt-parent = <&gic>;
 685                         interrupts = <0 16 4>;
 686                         interrupt-controller;
 687                         #interrupt-cells = <2>;
 688                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 689                         gpio-controller;
 690                         power-domains = <&pd_gpio>;
 691                 };
 692
 693                 i2c0: i2c@ff020000 {
 694                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 695                         status = "disabled";
 696                         interrupt-parent = <&gic>;
 697                         interrupts = <0 17 4>;
 698                         reg = <0x0 0xff020000 0x0 0x1000>;
 699                         #address-cells = <1>;
 700                         #size-cells = <0>;
 701                         power-domains = <&pd_i2c0>;
 702                 };
 703
 704                 i2c1: i2c@ff030000 {
 705                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 706                         status = "disabled";
 707                         interrupt-parent = <&gic>;
 708                         interrupts = <0 18 4>;
 709                         reg = <0x0 0xff030000 0x0 0x1000>;
 710                         #address-cells = <1>;
 711                         #size-cells = <0>;
 712                         power-domains = <&pd_i2c1>;
 713                 };
 714
 715                 ocm: memory-controller@ff960000 {
 716                         compatible = "xlnx,zynqmp-ocmc-1.0";
 717                         reg = <0x0 0xff960000 0x0 0x1000>;
 718                         interrupt-parent = <&gic>;
 719                         interrupts = <0 10 4>;
 720                 };
 721
 722                 pcie: pcie@fd0e0000 {
 723                         compatible = "xlnx,nwl-pcie-2.11";
 724                         status = "disabled";
 725                         #address-cells = <3>;
 726                         #size-cells = <2>;
 727                         #interrupt-cells = <1>;
 728                         msi-controller;
 729                         device_type = "pci";
 730                         interrupt-parent = <&gic>;
 731                         interrupts = <0 118 4>,
 732                                      <0 117 4>,
 733                                      <0 116 4>,
 734                                      <0 115 4>, /* MSI_1 [63...32] */
 735                                      <0 114 4>; /* MSI_0 [31...0] */
 736                         interrupt-names = "misc","dummy","intx", "msi1", "msi0";
 737                         msi-parent = <&pcie>;
 738                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 739                               <0x0 0xfd480000 0x0 0x1000>,
 740                               <0x80 0x00000000 0x0 0x1000000>;
 741                         reg-names = "breg", "pcireg", "cfg";
 742                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
 743                                   0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 744                         bus-range = <0x00 0xff>;
 745                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 746                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 747                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 748                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 749                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 750                         power-domains = <&pd_pcie>;
 751                         pcie_intc: legacy-interrupt-controller {
 752                                 interrupt-controller;
 753                                 #address-cells = <0>;
 754                                 #interrupt-cells = <1>;
 755                         };
 756                 };
 757
 758                 qspi: spi@ff0f0000 {
 759                         compatible = "xlnx,zynqmp-qspi-1.0";
 760                         status = "disabled";
 761                         clock-names = "ref_clk", "pclk";
 762                         interrupts = <0 15 4>;
 763                         interrupt-parent = <&gic>;
 764                         num-cs = <1>;
 765                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 766                               <0x0 0xc0000000 0x0 0x8000000>;
 767                         #address-cells = <1>;
 768                         #size-cells = <0>;
 769                         #stream-id-cells = <1>;
 770                         iommus = <&smmu 0x873>;
 771                         power-domains = <&pd_qspi>;
 772                 };
 773
 774                 rtc: rtc@ffa60000 {
 775                         compatible = "xlnx,zynqmp-rtc";
 776                         status = "disabled";
 777                         reg = <0x0 0xffa60000 0x0 0x100>;
 778                         interrupt-parent = <&gic>;
 779                         interrupts = <0 26 4>, <0 27 4>;
 780                         interrupt-names = "alarm", "sec";
 781                         calibration = <0x8000>;
 782                 };
 783
 784                 serdes: zynqmp_phy@fd400000 {
 785                         compatible = "xlnx,zynqmp-psgtr";
 786                         status = "disabled";
 787                         reg = <0x0 0xfd400000 0x0 0x40000>,
 788                               <0x0 0xfd3d0000 0x0 0x1000>,
 789                               <0x0 0xfd1a0000 0x0 0x1000>,
 790                               <0x0 0xff5e0000 0x0 0x1000>;
 791                         reg-names = "serdes", "siou", "fpd", "lpd";
 792                         nvmem-cells = <&soc_revision>;
 793                         nvmem-cell-names = "soc_revision";
 794                         resets = <&rst 16>, <&rst 59>, <&rst 60>,
 795                                  <&rst 61>, <&rst 62>, <&rst 63>,
 796                                  <&rst 64>, <&rst 3>, <&rst 29>,
 797                                  <&rst 30>, <&rst 31>, <&rst 32>;
 798                         reset-names = "sata_rst", "usb0_crst", "usb1_crst",
 799                                       "usb0_hibrst", "usb1_hibrst", "usb0_apbrst",
 800                                       "usb1_apbrst", "dp_rst", "gem0_rst",
 801                                       "gem1_rst", "gem2_rst", "gem3_rst";
 802                         lane0: lane0 {
 803                                 #phy-cells = <4>;
 804                         };
 805                         lane1: lane1 {
 806                                 #phy-cells = <4>;
 807                         };
 808                         lane2: lane2 {
 809                                 #phy-cells = <4>;
 810                         };
 811                         lane3: lane3 {
 812                                 #phy-cells = <4>;
 813                         };
 814                 };
 815
 816                 sata: ahci@fd0c0000 {
 817                         compatible = "ceva,ahci-1v84";
 818                         status = "disabled";
 819                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 820                         interrupt-parent = <&gic>;
 821                         interrupts = <0 133 4>;
 822                         power-domains = <&pd_sata>;
 823                         #stream-id-cells = <4>;
 824                         iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
 825                                  <&smmu 0x4c2>, <&smmu 0x4c3>;
 826                         /* dma-coherent; */
 827                 };
 828
 829                 sdhci0: sdhci@ff160000 {
 830                         u-boot,dm-pre-reloc;
 831                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 832                         status = "disabled";
 833                         interrupt-parent = <&gic>;
 834                         interrupts = <0 48 4>;
 835                         reg = <0x0 0xff160000 0x0 0x1000>;
 836                         clock-names = "clk_xin", "clk_ahb";
 837                         xlnx,device_id = <0>;
 838                         #stream-id-cells = <1>;
 839                         iommus = <&smmu 0x870>;
 840                         power-domains = <&pd_sd0>;
 841                 };
 842
 843                 sdhci1: sdhci@ff170000 {
 844                         u-boot,dm-pre-reloc;
 845                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 846                         status = "disabled";
 847                         interrupt-parent = <&gic>;
 848                         interrupts = <0 49 4>;
 849                         reg = <0x0 0xff170000 0x0 0x1000>;
 850                         clock-names = "clk_xin", "clk_ahb";
 851                         xlnx,device_id = <1>;
 852                         #stream-id-cells = <1>;
 853                         iommus = <&smmu 0x871>;
 854                         power-domains = <&pd_sd1>;
 855                 };
 856
 857                 pinctrl0: pinctrl@ff180000 {
 858                         compatible = "xlnx,pinctrl-zynqmp";
 859                         status = "disabled";
 860                         reg = <0x0 0xff180000 0x0 0x1000>;
 861                 };
 862
 863                 smmu: smmu@fd800000 {
 864                         compatible = "arm,mmu-500";
 865                         reg = <0x0 0xfd800000 0x0 0x20000>;
 866                         #iommu-cells = <1>;
 867                         status = "disabled";
 868                         #global-interrupts = <1>;
 869                         interrupt-parent = <&gic>;
 870                         interrupts = <0 155 4>,
 871                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 872                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 873                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 874                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 875                 };
 876
 877                 spi0: spi@ff040000 {
 878                         compatible = "cdns,spi-r1p6";
 879                         status = "disabled";
 880                         interrupt-parent = <&gic>;
 881                         interrupts = <0 19 4>;
 882                         reg = <0x0 0xff040000 0x0 0x1000>;
 883                         clock-names = "ref_clk", "pclk";
 884                         #address-cells = <1>;
 885                         #size-cells = <0>;
 886                         power-domains = <&pd_spi0>;
 887                 };
 888
 889                 spi1: spi@ff050000 {
 890                         compatible = "cdns,spi-r1p6";
 891                         status = "disabled";
 892                         interrupt-parent = <&gic>;
 893                         interrupts = <0 20 4>;
 894                         reg = <0x0 0xff050000 0x0 0x1000>;
 895                         clock-names = "ref_clk", "pclk";
 896                         #address-cells = <1>;
 897                         #size-cells = <0>;
 898                         power-domains = <&pd_spi1>;
 899                 };
 900
 901                 ttc0: timer@ff110000 {
 902                         compatible = "cdns,ttc";
 903                         status = "disabled";
 904                         interrupt-parent = <&gic>;
 905                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 906                         reg = <0x0 0xff110000 0x0 0x1000>;
 907                         timer-width = <32>;
 908                         power-domains = <&pd_ttc0>;
 909                 };
 910
 911                 ttc1: timer@ff120000 {
 912                         compatible = "cdns,ttc";
 913                         status = "disabled";
 914                         interrupt-parent = <&gic>;
 915                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 916                         reg = <0x0 0xff120000 0x0 0x1000>;
 917                         timer-width = <32>;
 918                         power-domains = <&pd_ttc1>;
 919                 };
 920
 921                 ttc2: timer@ff130000 {
 922                         compatible = "cdns,ttc";
 923                         status = "disabled";
 924                         interrupt-parent = <&gic>;
 925                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 926                         reg = <0x0 0xff130000 0x0 0x1000>;
 927                         timer-width = <32>;
 928                         power-domains = <&pd_ttc2>;
 929                 };
 930
 931                 ttc3: timer@ff140000 {
 932                         compatible = "cdns,ttc";
 933                         status = "disabled";
 934                         interrupt-parent = <&gic>;
 935                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 936                         reg = <0x0 0xff140000 0x0 0x1000>;
 937                         timer-width = <32>;
 938                         power-domains = <&pd_ttc3>;
 939                 };
 940
 941                 uart0: serial@ff000000 {
 942                         u-boot,dm-pre-reloc;
 943                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 944                         status = "disabled";
 945                         interrupt-parent = <&gic>;
 946                         interrupts = <0 21 4>;
 947                         reg = <0x0 0xff000000 0x0 0x1000>;
 948                         clock-names = "uart_clk", "pclk";
 949                         power-domains = <&pd_uart0>;
 950                 };
 951
 952                 uart1: serial@ff010000 {
 953                         u-boot,dm-pre-reloc;
 954                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 955                         status = "disabled";
 956                         interrupt-parent = <&gic>;
 957                         interrupts = <0 22 4>;
 958                         reg = <0x0 0xff010000 0x0 0x1000>;
 959                         clock-names = "uart_clk", "pclk";
 960                         power-domains = <&pd_uart1>;
 961                 };
 962
 963                 usb0: usb0 {
 964                         #address-cells = <2>;
 965                         #size-cells = <2>;
 966                         status = "disabled";
 967                         compatible = "xlnx,zynqmp-dwc3";
 968                         clock-names = "bus_clk", "ref_clk";
 969                         clocks = <&clk125>, <&clk125>;
 970                         #stream-id-cells = <1>;
 971                         iommus = <&smmu 0x860>;
 972                         power-domains = <&pd_usb0>;
 973                         ranges;
 974
 975                         dwc3_0: dwc3@fe200000 {
 976                                 compatible = "snps,dwc3";
 977                                 status = "disabled";
 978                                 reg = <0x0 0xfe200000 0x0 0x40000>;
 979                                 interrupt-parent = <&gic>;
 980                                 interrupts = <0 65 4>;
 981                                 /* snps,quirk-frame-length-adjustment = <0x20>; */
 982                                 snps,refclk_fladj;
 983                         };
 984                 };
 985
 986                 usb1: usb1 {
 987                         #address-cells = <2>;
 988                         #size-cells = <2>;
 989                         status = "disabled";
 990                         compatible = "xlnx,zynqmp-dwc3";
 991                         clock-names = "bus_clk", "ref_clk";
 992                         clocks = <&clk125>, <&clk125>;
 993                         #stream-id-cells = <1>;
 994                         iommus = <&smmu 0x861>;
 995                         power-domains = <&pd_usb1>;
 996                         ranges;
 997
 998                         dwc3_1: dwc3@fe300000 {
 999                                 compatible = "snps,dwc3";
1000                                 status = "disabled";
1001                                 reg = <0x0 0xfe300000 0x0 0x40000>;
1002                                 interrupt-parent = <&gic>;
1003                                 interrupts = <0 70 4>;
1004                                 /* snps,quirk-frame-length-adjustment = <0x20>; */
1005                                 snps,refclk_fladj;
1006                         };
1007                 };
1008
1009                 watchdog0: watchdog@fd4d0000 {
1010                         compatible = "cdns,wdt-r1p2";
1011                         status = "disabled";
1012                         interrupt-parent = <&gic>;
1013                         interrupts = <0 113 1>;
1014                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
1015                         timeout-sec = <10>;
1016                 };
1017
1018                 xilinx_drm: xilinx_drm {
1019                         compatible = "xlnx,drm";
1020                         status = "disabled";
1021                         xlnx,encoder-slave = <&xlnx_dp>;
1022                         xlnx,connector-type = "DisplayPort";
1023                         xlnx,dp-sub = <&xlnx_dp_sub>;
1024                         planes {
1025                                 xlnx,pixel-format = "rgb565";
1026                                 plane0 {
1027                                         dmas = <&xlnx_dpdma 3>;
1028                                         dma-names = "dma0";
1029                                 };
1030                                 plane1 {
1031                                         dmas = <&xlnx_dpdma 0>,
1032                                                <&xlnx_dpdma 1>,
1033                                                <&xlnx_dpdma 2>;
1034                                         dma-names = "dma0", "dma1", "dma2";
1035                                 };
1036                         };
1037                 };
1038
1039                 xlnx_dp: dp@fd4a0000 {
1040                         compatible = "xlnx,v-dp";
1041                         status = "disabled";
1042                         reg = <0x0 0xfd4a0000 0x0 0x1000>;
1043                         interrupts = <0 119 4>;
1044                         interrupt-parent = <&gic>;
1045                         clock-names = "aclk", "aud_clk";
1046                         power-domains = <&pd_dp>;
1047                         xlnx,dp-version = "v1.2";
1048                         xlnx,max-lanes = <2>;
1049                         xlnx,max-link-rate = <540000>;
1050                         xlnx,max-bpc = <16>;
1051                         xlnx,enable-ycrcb;
1052                         xlnx,colormetry = "rgb";
1053                         xlnx,bpc = <8>;
1054                         xlnx,audio-chan = <2>;
1055                         xlnx,dp-sub = <&xlnx_dp_sub>;
1056                         xlnx,max-pclock-frequency = <300000>;
1057                 };
1058
1059                 xlnx_dp_snd_card: dp_snd_card {
1060                         compatible = "xlnx,dp-snd-card";
1061                         status = "disabled";
1062                         xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
1063                         xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
1064                 };
1065
1066                 xlnx_dp_snd_codec0: dp_snd_codec0 {
1067                         compatible = "xlnx,dp-snd-codec";
1068                         status = "disabled";
1069                         clock-names = "aud_clk";
1070                 };
1071
1072                 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
1073                         compatible = "xlnx,dp-snd-pcm";
1074                         status = "disabled";
1075                         dmas = <&xlnx_dpdma 4>;
1076                         dma-names = "tx";
1077                 };
1078
1079                 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
1080                         compatible = "xlnx,dp-snd-pcm";
1081                         status = "disabled";
1082                         dmas = <&xlnx_dpdma 5>;
1083                         dma-names = "tx";
1084                 };
1085
1086                 xlnx_dp_sub: dp_sub@fd4aa000 {
1087                         compatible = "xlnx,dp-sub";
1088                         status = "disabled";
1089                         reg = <0x0 0xfd4aa000 0x0 0x1000>,
1090                               <0x0 0xfd4ab000 0x0 0x1000>,
1091                               <0x0 0xfd4ac000 0x0 0x1000>;
1092                         reg-names = "blend", "av_buf", "aud";
1093                         xlnx,output-fmt = "rgb";
1094                         xlnx,vid-fmt = "yuyv";
1095                         xlnx,gfx-fmt = "rgb565";
1096                         power-domains = <&pd_dp>;
1097                 };
1098
1099                 xlnx_dpdma: dma@fd4c0000 {
1100                         compatible = "xlnx,dpdma";
1101                         status = "disabled";
1102                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
1103                         interrupts = <0 122 4>;
1104                         interrupt-parent = <&gic>;
1105                         clock-names = "axi_clk";
1106                         power-domains = <&pd_dp>;
1107                         dma-channels = <6>;
1108                         #dma-cells = <1>;
1109                         dma-video0channel {
1110                                 compatible = "xlnx,video0";
1111                         };
1112                         dma-video1channel {
1113                                 compatible = "xlnx,video1";
1114                         };
1115                         dma-video2channel {
1116                                 compatible = "xlnx,video2";
1117                         };
1118                         dma-graphicschannel {
1119                                 compatible = "xlnx,graphics";
1120                         };
1121                         dma-audio0channel {
1122                                 compatible = "xlnx,audio0";
1123                         };
1124                         dma-audio1channel {
1125                                 compatible = "xlnx,audio1";
1126                         };
1127                 };
1128         };
1129 };