git.sur5r.net Git - u-boot/blob - arch/arm/dts/zynqmp.dtsi

   1 /*
   2  * dts file for Xilinx ZynqMP
   3  *
   4  * (C) Copyright 2014 - 2015, Xilinx, Inc.
   5  *
   6  * Michal Simek <michal.simek@xilinx.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 / {
  12         compatible = "xlnx,zynqmp";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu0: cpu@0 {
  21                         compatible = "arm,cortex-a53", "arm,armv8";
  22                         device_type = "cpu";
  23                         enable-method = "psci";
  24                         operating-points-v2 = <&cpu_opp_table>;
  25                         reg = <0x0>;
  26                         cpu-idle-states = <&CPU_SLEEP_0>;
  27                 };
  28
  29                 cpu1: cpu@1 {
  30                         compatible = "arm,cortex-a53", "arm,armv8";
  31                         device_type = "cpu";
  32                         enable-method = "psci";
  33                         reg = <0x1>;
  34                         operating-points-v2 = <&cpu_opp_table>;
  35                         cpu-idle-states = <&CPU_SLEEP_0>;
  36                 };
  37
  38                 cpu2: cpu@2 {
  39                         compatible = "arm,cortex-a53", "arm,armv8";
  40                         device_type = "cpu";
  41                         enable-method = "psci";
  42                         reg = <0x2>;
  43                         operating-points-v2 = <&cpu_opp_table>;
  44                         cpu-idle-states = <&CPU_SLEEP_0>;
  45                 };
  46
  47                 cpu3: cpu@3 {
  48                         compatible = "arm,cortex-a53", "arm,armv8";
  49                         device_type = "cpu";
  50                         enable-method = "psci";
  51                         reg = <0x3>;
  52                         operating-points-v2 = <&cpu_opp_table>;
  53                         cpu-idle-states = <&CPU_SLEEP_0>;
  54                 };
  55
  56                 idle-states {
  57                         entry-method = "arm,psci";
  58
  59                         CPU_SLEEP_0: cpu-sleep-0 {
  60                                 compatible = "arm,idle-state";
  61                                 arm,psci-suspend-param = <0x40000000>;
  62                                 local-timer-stop;
  63                                 entry-latency-us = <300>;
  64                                 exit-latency-us = <600>;
  65                                 min-residency-us = <10000>;
  66                         };
  67                 };
  68         };
  69
  70         cpu_opp_table: cpu_opp_table {
  71                 compatible = "operating-points-v2";
  72                 opp-shared;
  73                 opp00 {
  74                         opp-hz = /bits/ 64 <1199999988>;
  75                         opp-microvolt = <1000000>;
  76                         clock-latency-ns = <500000>;
  77                 };
  78                 opp01 {
  79                         opp-hz = /bits/ 64 <599999994>;
  80                         opp-microvolt = <1000000>;
  81                         clock-latency-ns = <500000>;
  82                 };
  83                 opp02 {
  84                         opp-hz = /bits/ 64 <399999996>;
  85                         opp-microvolt = <1000000>;
  86                         clock-latency-ns = <500000>;
  87                 };
  88                 opp03 {
  89                         opp-hz = /bits/ 64 <299999997>;
  90                         opp-microvolt = <1000000>;
  91                         clock-latency-ns = <500000>;
  92                 };
  93         };
  94
  95         dcc: dcc {
  96                 compatible = "arm,dcc";
  97                 status = "disabled";
  98                 u-boot,dm-pre-reloc;
  99         };
 100
 101         power-domains {
 102                 compatible = "xlnx,zynqmp-genpd";
 103
 104                 pd_usb0: pd-usb0 {
 105                         #power-domain-cells = <0x0>;
 106                         pd-id = <0x16>;
 107                 };
 108
 109                 pd_usb1: pd-usb1 {
 110                         #power-domain-cells = <0x0>;
 111                         pd-id = <0x17>;
 112                 };
 113
 114                 pd_sata: pd-sata {
 115                         #power-domain-cells = <0x0>;
 116                         pd-id = <0x1c>;
 117                 };
 118
 119                 pd_spi0: pd-spi0 {
 120                         #power-domain-cells = <0x0>;
 121                         pd-id = <0x23>;
 122                 };
 123
 124                 pd_spi1: pd-spi1 {
 125                         #power-domain-cells = <0x0>;
 126                         pd-id = <0x24>;
 127                 };
 128
 129                 pd_uart0: pd-uart0 {
 130                         #power-domain-cells = <0x0>;
 131                         pd-id = <0x21>;
 132                 };
 133
 134                 pd_uart1: pd-uart1 {
 135                         #power-domain-cells = <0x0>;
 136                         pd-id = <0x22>;
 137                 };
 138
 139                 pd_eth0: pd-eth0 {
 140                         #power-domain-cells = <0x0>;
 141                         pd-id = <0x1d>;
 142                 };
 143
 144                 pd_eth1: pd-eth1 {
 145                         #power-domain-cells = <0x0>;
 146                         pd-id = <0x1e>;
 147                 };
 148
 149                 pd_eth2: pd-eth2 {
 150                         #power-domain-cells = <0x0>;
 151                         pd-id = <0x1f>;
 152                 };
 153
 154                 pd_eth3: pd-eth3 {
 155                         #power-domain-cells = <0x0>;
 156                         pd-id = <0x20>;
 157                 };
 158
 159                 pd_i2c0: pd-i2c0 {
 160                         #power-domain-cells = <0x0>;
 161                         pd-id = <0x25>;
 162                 };
 163
 164                 pd_i2c1: pd-i2c1 {
 165                         #power-domain-cells = <0x0>;
 166                         pd-id = <0x26>;
 167                 };
 168
 169                 pd_dp: pd-dp {
 170                         #power-domain-cells = <0x0>;
 171                         pd-id = <0x29>;
 172                 };
 173
 174                 pd_gdma: pd-gdma {
 175                         #power-domain-cells = <0x0>;
 176                         pd-id = <0x2a>;
 177                 };
 178
 179                 pd_adma: pd-adma {
 180                         #power-domain-cells = <0x0>;
 181                         pd-id = <0x2b>;
 182                 };
 183
 184                 pd_ttc0: pd-ttc0 {
 185                         #power-domain-cells = <0x0>;
 186                         pd-id = <0x18>;
 187                 };
 188
 189                 pd_ttc1: pd-ttc1 {
 190                         #power-domain-cells = <0x0>;
 191                         pd-id = <0x19>;
 192                 };
 193
 194                 pd_ttc2: pd-ttc2 {
 195                         #power-domain-cells = <0x0>;
 196                         pd-id = <0x1a>;
 197                 };
 198
 199                 pd_ttc3: pd-ttc3 {
 200                         #power-domain-cells = <0x0>;
 201                         pd-id = <0x1b>;
 202                 };
 203
 204                 pd_sd0: pd-sd0 {
 205                         #power-domain-cells = <0x0>;
 206                         pd-id = <0x27>;
 207                 };
 208
 209                 pd_sd1: pd-sd1 {
 210                         #power-domain-cells = <0x0>;
 211                         pd-id = <0x28>;
 212                 };
 213
 214                 pd_nand: pd-nand {
 215                         #power-domain-cells = <0x0>;
 216                         pd-id = <0x2c>;
 217                 };
 218
 219                 pd_qspi: pd-qspi {
 220                         #power-domain-cells = <0x0>;
 221                         pd-id = <0x2d>;
 222                 };
 223
 224                 pd_gpio: pd-gpio {
 225                         #power-domain-cells = <0x0>;
 226                         pd-id = <0x2e>;
 227                 };
 228
 229                 pd_can0: pd-can0 {
 230                         #power-domain-cells = <0x0>;
 231                         pd-id = <0x2f>;
 232                 };
 233
 234                 pd_can1: pd-can1 {
 235                         #power-domain-cells = <0x0>;
 236                         pd-id = <0x30>;
 237                 };
 238
 239                 pd_pcie: pd-pcie {
 240                         #power-domain-cells = <0x0>;
 241                         pd-id = <0x3b>;
 242                 };
 243
 244                 pd_gpu: pd-gpu {
 245                         #power-domain-cells = <0x0>;
 246                         pd-id = <0x3a 0x14 0x15>;
 247                 };
 248         };
 249
 250         pmu {
 251                 compatible = "arm,armv8-pmuv3";
 252                 interrupt-parent = <&gic>;
 253                 interrupts = <0 143 4>,
 254                              <0 144 4>,
 255                              <0 145 4>,
 256                              <0 146 4>;
 257         };
 258
 259         psci {
 260                 compatible = "arm,psci-0.2";
 261                 method = "smc";
 262         };
 263
 264         firmware {
 265                 compatible = "xlnx,zynqmp-pm";
 266                 method = "smc";
 267                 interrupt-parent = <&gic>;
 268                 interrupts = <0 35 4>;
 269         };
 270
 271         timer {
 272                 compatible = "arm,armv8-timer";
 273                 interrupt-parent = <&gic>;
 274                 interrupts = <1 13 0xf08>,
 275                              <1 14 0xf08>,
 276                              <1 11 0xf08>,
 277                              <1 10 0xf08>;
 278         };
 279
 280         edac {
 281                 compatible = "arm,cortex-a53-edac";
 282         };
 283
 284         fpga_full: fpga-full {
 285                 compatible = "fpga-region";
 286                 fpga-mgr = <&pcap>;
 287                 #address-cells = <2>;
 288                 #size-cells = <2>;
 289         };
 290
 291         pcap: pcap {
 292                 compatible = "xlnx,zynqmp-pcap-fpga";
 293         };
 294
 295         amba_apu: amba_apu@0 {
 296                 compatible = "simple-bus";
 297                 #address-cells = <2>;
 298                 #size-cells = <1>;
 299                 ranges = <0 0 0 0 0xffffffff>;
 300
 301                 gic: interrupt-controller@f9010000 {
 302                         compatible = "arm,gic-400", "arm,cortex-a15-gic";
 303                         #interrupt-cells = <3>;
 304                         reg = <0x0 0xf9010000 0x10000>,
 305                               <0x0 0xf9020000 0x20000>,
 306                               <0x0 0xf9040000 0x20000>,
 307                               <0x0 0xf9060000 0x20000>;
 308                         interrupt-controller;
 309                         interrupt-parent = <&gic>;
 310                         interrupts = <1 9 0xf04>;
 311                 };
 312         };
 313
 314         amba: amba {
 315                 compatible = "simple-bus";
 316                 u-boot,dm-pre-reloc;
 317                 #address-cells = <2>;
 318                 #size-cells = <2>;
 319                 ranges;
 320
 321                 can0: can@ff060000 {
 322                         compatible = "xlnx,zynq-can-1.0";
 323                         status = "disabled";
 324                         clock-names = "can_clk", "pclk";
 325                         reg = <0x0 0xff060000 0x0 0x1000>;
 326                         interrupts = <0 23 4>;
 327                         interrupt-parent = <&gic>;
 328                         tx-fifo-depth = <0x40>;
 329                         rx-fifo-depth = <0x40>;
 330                         power-domains = <&pd_can0>;
 331                 };
 332
 333                 can1: can@ff070000 {
 334                         compatible = "xlnx,zynq-can-1.0";
 335                         status = "disabled";
 336                         clock-names = "can_clk", "pclk";
 337                         reg = <0x0 0xff070000 0x0 0x1000>;
 338                         interrupts = <0 24 4>;
 339                         interrupt-parent = <&gic>;
 340                         tx-fifo-depth = <0x40>;
 341                         rx-fifo-depth = <0x40>;
 342                         power-domains = <&pd_can1>;
 343                 };
 344
 345                 cci: cci@fd6e0000 {
 346                         compatible = "arm,cci-400";
 347                         reg = <0x0 0xfd6e0000 0x0 0x9000>;
 348                         ranges = <0x0 0x0 0xfd6e0000 0x10000>;
 349                         #address-cells = <1>;
 350                         #size-cells = <1>;
 351
 352                         pmu@9000 {
 353                                 compatible = "arm,cci-400-pmu,r1";
 354                                 reg = <0x9000 0x5000>;
 355                                 interrupt-parent = <&gic>;
 356                                 interrupts = <0 123 4>,
 357                                              <0 123 4>,
 358                                              <0 123 4>,
 359                                              <0 123 4>,
 360                                              <0 123 4>;
 361                         };
 362                 };
 363
 364                 /* GDMA */
 365                 fpd_dma_chan1: dma@fd500000 {
 366                         status = "disabled";
 367                         compatible = "xlnx,zynqmp-dma-1.0";
 368                         reg = <0x0 0xfd500000 0x0 0x1000>;
 369                         interrupt-parent = <&gic>;
 370                         interrupts = <0 124 4>;
 371                         clock-names = "clk_main", "clk_apb";
 372                         xlnx,bus-width = <128>;
 373                         #stream-id-cells = <1>;
 374                         iommus = <&smmu 0x14e8>;
 375                         power-domains = <&pd_gdma>;
 376                 };
 377
 378                 fpd_dma_chan2: dma@fd510000 {
 379                         status = "disabled";
 380                         compatible = "xlnx,zynqmp-dma-1.0";
 381                         reg = <0x0 0xfd510000 0x0 0x1000>;
 382                         interrupt-parent = <&gic>;
 383                         interrupts = <0 125 4>;
 384                         clock-names = "clk_main", "clk_apb";
 385                         xlnx,bus-width = <128>;
 386                         #stream-id-cells = <1>;
 387                         iommus = <&smmu 0x14e9>;
 388                         power-domains = <&pd_gdma>;
 389                 };
 390
 391                 fpd_dma_chan3: dma@fd520000 {
 392                         status = "disabled";
 393                         compatible = "xlnx,zynqmp-dma-1.0";
 394                         reg = <0x0 0xfd520000 0x0 0x1000>;
 395                         interrupt-parent = <&gic>;
 396                         interrupts = <0 126 4>;
 397                         clock-names = "clk_main", "clk_apb";
 398                         xlnx,bus-width = <128>;
 399                         #stream-id-cells = <1>;
 400                         iommus = <&smmu 0x14ea>;
 401                         power-domains = <&pd_gdma>;
 402                 };
 403
 404                 fpd_dma_chan4: dma@fd530000 {
 405                         status = "disabled";
 406                         compatible = "xlnx,zynqmp-dma-1.0";
 407                         reg = <0x0 0xfd530000 0x0 0x1000>;
 408                         interrupt-parent = <&gic>;
 409                         interrupts = <0 127 4>;
 410                         clock-names = "clk_main", "clk_apb";
 411                         xlnx,bus-width = <128>;
 412                         #stream-id-cells = <1>;
 413                         iommus = <&smmu 0x14eb>;
 414                         power-domains = <&pd_gdma>;
 415                 };
 416
 417                 fpd_dma_chan5: dma@fd540000 {
 418                         status = "disabled";
 419                         compatible = "xlnx,zynqmp-dma-1.0";
 420                         reg = <0x0 0xfd540000 0x0 0x1000>;
 421                         interrupt-parent = <&gic>;
 422                         interrupts = <0 128 4>;
 423                         clock-names = "clk_main", "clk_apb";
 424                         xlnx,bus-width = <128>;
 425                         #stream-id-cells = <1>;
 426                         iommus = <&smmu 0x14ec>;
 427                         power-domains = <&pd_gdma>;
 428                 };
 429
 430                 fpd_dma_chan6: dma@fd550000 {
 431                         status = "disabled";
 432                         compatible = "xlnx,zynqmp-dma-1.0";
 433                         reg = <0x0 0xfd550000 0x0 0x1000>;
 434                         interrupt-parent = <&gic>;
 435                         interrupts = <0 129 4>;
 436                         clock-names = "clk_main", "clk_apb";
 437                         xlnx,bus-width = <128>;
 438                         #stream-id-cells = <1>;
 439                         iommus = <&smmu 0x14ed>;
 440                         power-domains = <&pd_gdma>;
 441                 };
 442
 443                 fpd_dma_chan7: dma@fd560000 {
 444                         status = "disabled";
 445                         compatible = "xlnx,zynqmp-dma-1.0";
 446                         reg = <0x0 0xfd560000 0x0 0x1000>;
 447                         interrupt-parent = <&gic>;
 448                         interrupts = <0 130 4>;
 449                         clock-names = "clk_main", "clk_apb";
 450                         xlnx,bus-width = <128>;
 451                         #stream-id-cells = <1>;
 452                         iommus = <&smmu 0x14ee>;
 453                         power-domains = <&pd_gdma>;
 454                 };
 455
 456                 fpd_dma_chan8: dma@fd570000 {
 457                         status = "disabled";
 458                         compatible = "xlnx,zynqmp-dma-1.0";
 459                         reg = <0x0 0xfd570000 0x0 0x1000>;
 460                         interrupt-parent = <&gic>;
 461                         interrupts = <0 131 4>;
 462                         clock-names = "clk_main", "clk_apb";
 463                         xlnx,bus-width = <128>;
 464                         #stream-id-cells = <1>;
 465                         iommus = <&smmu 0x14ef>;
 466                         power-domains = <&pd_gdma>;
 467                 };
 468
 469                 gpu: gpu@fd4b0000 {
 470                         status = "disabled";
 471                         compatible = "arm,mali-400", "arm,mali-utgard";
 472                         reg = <0x0 0xfd4b0000 0x0 0x10000>;
 473                         interrupt-parent = <&gic>;
 474                         interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>;
 475                         interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1";
 476                         clock-names = "gpu", "gpu_pp0", "gpu_pp1";
 477                         power-domains = <&pd_gpu>;
 478                 };
 479
 480                 /* LPDDMA default allows only secured access. inorder to enable
 481                  * These dma channels, Users should ensure that these dma
 482                  * Channels are allowed for non secure access.
 483                  */
 484                 lpd_dma_chan1: dma@ffa80000 {
 485                         status = "disabled";
 486                         compatible = "xlnx,zynqmp-dma-1.0";
 487                         clock-names = "clk_main", "clk_apb";
 488                         reg = <0x0 0xffa80000 0x0 0x1000>;
 489                         interrupt-parent = <&gic>;
 490                         interrupts = <0 77 4>;
 491                         xlnx,bus-width = <64>;
 492                         #stream-id-cells = <1>;
 493                         iommus = <&smmu 0x868>;
 494                         power-domains = <&pd_adma>;
 495                 };
 496
 497                 lpd_dma_chan2: dma@ffa90000 {
 498                         status = "disabled";
 499                         compatible = "xlnx,zynqmp-dma-1.0";
 500                         clock-names = "clk_main", "clk_apb";
 501                         reg = <0x0 0xffa90000 0x0 0x1000>;
 502                         interrupt-parent = <&gic>;
 503                         interrupts = <0 78 4>;
 504                         xlnx,bus-width = <64>;
 505                         #stream-id-cells = <1>;
 506                         iommus = <&smmu 0x869>;
 507                         power-domains = <&pd_adma>;
 508                 };
 509
 510                 lpd_dma_chan3: dma@ffaa0000 {
 511                         status = "disabled";
 512                         compatible = "xlnx,zynqmp-dma-1.0";
 513                         clock-names = "clk_main", "clk_apb";
 514                         reg = <0x0 0xffaa0000 0x0 0x1000>;
 515                         interrupt-parent = <&gic>;
 516                         interrupts = <0 79 4>;
 517                         xlnx,bus-width = <64>;
 518                         #stream-id-cells = <1>;
 519                         iommus = <&smmu 0x86a>;
 520                         power-domains = <&pd_adma>;
 521                 };
 522
 523                 lpd_dma_chan4: dma@ffab0000 {
 524                         status = "disabled";
 525                         compatible = "xlnx,zynqmp-dma-1.0";
 526                         clock-names = "clk_main", "clk_apb";
 527                         reg = <0x0 0xffab0000 0x0 0x1000>;
 528                         interrupt-parent = <&gic>;
 529                         interrupts = <0 80 4>;
 530                         xlnx,bus-width = <64>;
 531                         #stream-id-cells = <1>;
 532                         iommus = <&smmu 0x86b>;
 533                         power-domains = <&pd_adma>;
 534                 };
 535
 536                 lpd_dma_chan5: dma@ffac0000 {
 537                         status = "disabled";
 538                         compatible = "xlnx,zynqmp-dma-1.0";
 539                         clock-names = "clk_main", "clk_apb";
 540                         reg = <0x0 0xffac0000 0x0 0x1000>;
 541                         interrupt-parent = <&gic>;
 542                         interrupts = <0 81 4>;
 543                         xlnx,bus-width = <64>;
 544                         #stream-id-cells = <1>;
 545                         iommus = <&smmu 0x86c>;
 546                         power-domains = <&pd_adma>;
 547                 };
 548
 549                 lpd_dma_chan6: dma@ffad0000 {
 550                         status = "disabled";
 551                         compatible = "xlnx,zynqmp-dma-1.0";
 552                         clock-names = "clk_main", "clk_apb";
 553                         reg = <0x0 0xffad0000 0x0 0x1000>;
 554                         interrupt-parent = <&gic>;
 555                         interrupts = <0 82 4>;
 556                         xlnx,bus-width = <64>;
 557                         #stream-id-cells = <1>;
 558                         iommus = <&smmu 0x86d>;
 559                         power-domains = <&pd_adma>;
 560                 };
 561
 562                 lpd_dma_chan7: dma@ffae0000 {
 563                         status = "disabled";
 564                         compatible = "xlnx,zynqmp-dma-1.0";
 565                         clock-names = "clk_main", "clk_apb";
 566                         reg = <0x0 0xffae0000 0x0 0x1000>;
 567                         interrupt-parent = <&gic>;
 568                         interrupts = <0 83 4>;
 569                         xlnx,bus-width = <64>;
 570                         #stream-id-cells = <1>;
 571                         iommus = <&smmu 0x86e>;
 572                         power-domains = <&pd_adma>;
 573                 };
 574
 575                 lpd_dma_chan8: dma@ffaf0000 {
 576                         status = "disabled";
 577                         compatible = "xlnx,zynqmp-dma-1.0";
 578                         clock-names = "clk_main", "clk_apb";
 579                         reg = <0x0 0xffaf0000 0x0 0x1000>;
 580                         interrupt-parent = <&gic>;
 581                         interrupts = <0 84 4>;
 582                         xlnx,bus-width = <64>;
 583                         #stream-id-cells = <1>;
 584                         iommus = <&smmu 0x86f>;
 585                         power-domains = <&pd_adma>;
 586                 };
 587
 588                 mc: memory-controller@fd070000 {
 589                         compatible = "xlnx,zynqmp-ddrc-2.40a";
 590                         reg = <0x0 0xfd070000 0x0 0x30000>;
 591                         interrupt-parent = <&gic>;
 592                         interrupts = <0 112 4>;
 593                 };
 594
 595                 nand0: nand@ff100000 {
 596                         compatible = "arasan,nfc-v3p10";
 597                         status = "disabled";
 598                         reg = <0x0 0xff100000 0x0 0x1000>;
 599                         clock-names = "clk_sys", "clk_flash";
 600                         interrupt-parent = <&gic>;
 601                         interrupts = <0 14 4>;
 602                         #address-cells = <2>;
 603                         #size-cells = <1>;
 604                         #stream-id-cells = <1>;
 605                         iommus = <&smmu 0x872>;
 606                         power-domains = <&pd_nand>;
 607                 };
 608
 609                 gem0: ethernet@ff0b0000 {
 610                         compatible = "cdns,zynqmp-gem";
 611                         status = "disabled";
 612                         interrupt-parent = <&gic>;
 613                         interrupts = <0 57 4>, <0 57 4>;
 614                         reg = <0x0 0xff0b0000 0x0 0x1000>;
 615                         clock-names = "pclk", "hclk", "tx_clk";
 616                         #address-cells = <1>;
 617                         #size-cells = <0>;
 618                         #stream-id-cells = <1>;
 619                         iommus = <&smmu 0x874>;
 620                         power-domains = <&pd_eth0>;
 621                 };
 622
 623                 gem1: ethernet@ff0c0000 {
 624                         compatible = "cdns,zynqmp-gem";
 625                         status = "disabled";
 626                         interrupt-parent = <&gic>;
 627                         interrupts = <0 59 4>, <0 59 4>;
 628                         reg = <0x0 0xff0c0000 0x0 0x1000>;
 629                         clock-names = "pclk", "hclk", "tx_clk";
 630                         #address-cells = <1>;
 631                         #size-cells = <0>;
 632                         #stream-id-cells = <1>;
 633                         iommus = <&smmu 0x875>;
 634                         power-domains = <&pd_eth1>;
 635                 };
 636
 637                 gem2: ethernet@ff0d0000 {
 638                         compatible = "cdns,zynqmp-gem";
 639                         status = "disabled";
 640                         interrupt-parent = <&gic>;
 641                         interrupts = <0 61 4>, <0 61 4>;
 642                         reg = <0x0 0xff0d0000 0x0 0x1000>;
 643                         clock-names = "pclk", "hclk", "tx_clk";
 644                         #address-cells = <1>;
 645                         #size-cells = <0>;
 646                         #stream-id-cells = <1>;
 647                         iommus = <&smmu 0x876>;
 648                         power-domains = <&pd_eth2>;
 649                 };
 650
 651                 gem3: ethernet@ff0e0000 {
 652                         compatible = "cdns,zynqmp-gem";
 653                         status = "disabled";
 654                         interrupt-parent = <&gic>;
 655                         interrupts = <0 63 4>, <0 63 4>;
 656                         reg = <0x0 0xff0e0000 0x0 0x1000>;
 657                         clock-names = "pclk", "hclk", "tx_clk";
 658                         #address-cells = <1>;
 659                         #size-cells = <0>;
 660                         #stream-id-cells = <1>;
 661                         iommus = <&smmu 0x877>;
 662                         power-domains = <&pd_eth3>;
 663                 };
 664
 665                 gpio: gpio@ff0a0000 {
 666                         compatible = "xlnx,zynqmp-gpio-1.0";
 667                         status = "disabled";
 668                         #gpio-cells = <0x2>;
 669                         interrupt-parent = <&gic>;
 670                         interrupts = <0 16 4>;
 671                         interrupt-controller;
 672                         #interrupt-cells = <2>;
 673                         reg = <0x0 0xff0a0000 0x0 0x1000>;
 674                         gpio-controller;
 675                         power-domains = <&pd_gpio>;
 676                 };
 677
 678                 i2c0: i2c@ff020000 {
 679                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 680                         status = "disabled";
 681                         interrupt-parent = <&gic>;
 682                         interrupts = <0 17 4>;
 683                         reg = <0x0 0xff020000 0x0 0x1000>;
 684                         #address-cells = <1>;
 685                         #size-cells = <0>;
 686                         power-domains = <&pd_i2c0>;
 687                 };
 688
 689                 i2c1: i2c@ff030000 {
 690                         compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
 691                         status = "disabled";
 692                         interrupt-parent = <&gic>;
 693                         interrupts = <0 18 4>;
 694                         reg = <0x0 0xff030000 0x0 0x1000>;
 695                         #address-cells = <1>;
 696                         #size-cells = <0>;
 697                         power-domains = <&pd_i2c1>;
 698                 };
 699
 700                 ocm: memory-controller@ff960000 {
 701                         compatible = "xlnx,zynqmp-ocmc-1.0";
 702                         reg = <0x0 0xff960000 0x0 0x1000>;
 703                         interrupt-parent = <&gic>;
 704                         interrupts = <0 10 4>;
 705                 };
 706
 707                 pcie: pcie@fd0e0000 {
 708                         compatible = "xlnx,nwl-pcie-2.11";
 709                         status = "disabled";
 710                         #address-cells = <3>;
 711                         #size-cells = <2>;
 712                         #interrupt-cells = <1>;
 713                         msi-controller;
 714                         device_type = "pci";
 715                         interrupt-parent = <&gic>;
 716                         interrupts = <0 118 4>,
 717                                      <0 117 4>,
 718                                      <0 116 4>,
 719                                      <0 115 4>, /* MSI_1 [63...32] */
 720                                      <0 114 4>; /* MSI_0 [31...0] */
 721                         interrupt-names = "misc","dummy","intx", "msi1", "msi0";
 722                         msi-parent = <&pcie>;
 723                         reg = <0x0 0xfd0e0000 0x0 0x1000>,
 724                               <0x0 0xfd480000 0x0 0x1000>,
 725                               <0x80 0x00000000 0x0 0x1000000>;
 726                         reg-names = "breg", "pcireg", "cfg";
 727                         ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
 728                                   0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
 729                         bus-range = <0x00 0xff>;
 730                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 731                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
 732                                         <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
 733                                         <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
 734                                         <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
 735                         power-domains = <&pd_pcie>;
 736                         pcie_intc: legacy-interrupt-controller {
 737                                 interrupt-controller;
 738                                 #address-cells = <0>;
 739                                 #interrupt-cells = <1>;
 740                         };
 741                 };
 742
 743                 qspi: spi@ff0f0000 {
 744                         compatible = "xlnx,zynqmp-qspi-1.0";
 745                         status = "disabled";
 746                         clock-names = "ref_clk", "pclk";
 747                         interrupts = <0 15 4>;
 748                         interrupt-parent = <&gic>;
 749                         num-cs = <1>;
 750                         reg = <0x0 0xff0f0000 0x0 0x1000>,
 751                               <0x0 0xc0000000 0x0 0x8000000>;
 752                         #address-cells = <1>;
 753                         #size-cells = <0>;
 754                         #stream-id-cells = <1>;
 755                         iommus = <&smmu 0x873>;
 756                         power-domains = <&pd_qspi>;
 757                 };
 758
 759                 rtc: rtc@ffa60000 {
 760                         compatible = "xlnx,zynqmp-rtc";
 761                         status = "disabled";
 762                         reg = <0x0 0xffa60000 0x0 0x100>;
 763                         interrupt-parent = <&gic>;
 764                         interrupts = <0 26 4>, <0 27 4>;
 765                         interrupt-names = "alarm", "sec";
 766                         calibration = <0x8000>;
 767                 };
 768
 769                 serdes: zynqmp_phy@fd400000 {
 770                         compatible = "xlnx,zynqmp-psgtr";
 771                         status = "disabled";
 772                         reg = <0x0 0xfd400000 0x0 0x40000>,
 773                               <0x0 0xfd3d0000 0x0 0x1000>,
 774                               <0x0 0xfd1a0000 0x0 0x1000>,
 775                               <0x0 0xff5e0000 0x0 0x1000>;
 776                         reg-names = "serdes", "siou", "fpd", "lpd";
 777                         xlnx,tx_termination_fix;
 778                         lane0: lane0 {
 779                                 #phy-cells = <4>;
 780                         };
 781                         lane1: lane1 {
 782                                 #phy-cells = <4>;
 783                         };
 784                         lane2: lane2 {
 785                                 #phy-cells = <4>;
 786                         };
 787                         lane3: lane3 {
 788                                 #phy-cells = <4>;
 789                         };
 790                 };
 791
 792                 sata: ahci@fd0c0000 {
 793                         compatible = "ceva,ahci-1v84";
 794                         status = "disabled";
 795                         reg = <0x0 0xfd0c0000 0x0 0x2000>;
 796                         interrupt-parent = <&gic>;
 797                         interrupts = <0 133 4>;
 798                         power-domains = <&pd_sata>;
 799                         #stream-id-cells = <4>;
 800                         iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
 801                                  <&smmu 0x4c2>, <&smmu 0x4c3>;
 802                         /* dma-coherent; */
 803                 };
 804
 805                 sdhci0: sdhci@ff160000 {
 806                         u-boot,dm-pre-reloc;
 807                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 808                         status = "disabled";
 809                         interrupt-parent = <&gic>;
 810                         interrupts = <0 48 4>;
 811                         reg = <0x0 0xff160000 0x0 0x1000>;
 812                         clock-names = "clk_xin", "clk_ahb";
 813                         xlnx,device_id = <0>;
 814                         #stream-id-cells = <1>;
 815                         iommus = <&smmu 0x870>;
 816                         power-domains = <&pd_sd0>;
 817                 };
 818
 819                 sdhci1: sdhci@ff170000 {
 820                         u-boot,dm-pre-reloc;
 821                         compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 822                         status = "disabled";
 823                         interrupt-parent = <&gic>;
 824                         interrupts = <0 49 4>;
 825                         reg = <0x0 0xff170000 0x0 0x1000>;
 826                         clock-names = "clk_xin", "clk_ahb";
 827                         xlnx,device_id = <1>;
 828                         #stream-id-cells = <1>;
 829                         iommus = <&smmu 0x871>;
 830                         power-domains = <&pd_sd1>;
 831                 };
 832
 833                 pinctrl0: pinctrl@ff180000 {
 834                         compatible = "xlnx,pinctrl-zynqmp";
 835                         status = "disabled";
 836                         reg = <0x0 0xff180000 0x0 0x1000>;
 837                 };
 838
 839                 smmu: smmu@fd800000 {
 840                         compatible = "arm,mmu-500";
 841                         reg = <0x0 0xfd800000 0x0 0x20000>;
 842                         #iommu-cells = <1>;
 843                         status = "disabled";
 844                         #global-interrupts = <1>;
 845                         interrupt-parent = <&gic>;
 846                         interrupts = <0 155 4>,
 847                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 848                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 849                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
 850                                 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
 851                 };
 852
 853                 spi0: spi@ff040000 {
 854                         compatible = "cdns,spi-r1p6";
 855                         status = "disabled";
 856                         interrupt-parent = <&gic>;
 857                         interrupts = <0 19 4>;
 858                         reg = <0x0 0xff040000 0x0 0x1000>;
 859                         clock-names = "ref_clk", "pclk";
 860                         #address-cells = <1>;
 861                         #size-cells = <0>;
 862                         power-domains = <&pd_spi0>;
 863                 };
 864
 865                 spi1: spi@ff050000 {
 866                         compatible = "cdns,spi-r1p6";
 867                         status = "disabled";
 868                         interrupt-parent = <&gic>;
 869                         interrupts = <0 20 4>;
 870                         reg = <0x0 0xff050000 0x0 0x1000>;
 871                         clock-names = "ref_clk", "pclk";
 872                         #address-cells = <1>;
 873                         #size-cells = <0>;
 874                         power-domains = <&pd_spi1>;
 875                 };
 876
 877                 ttc0: timer@ff110000 {
 878                         compatible = "cdns,ttc";
 879                         status = "disabled";
 880                         interrupt-parent = <&gic>;
 881                         interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
 882                         reg = <0x0 0xff110000 0x0 0x1000>;
 883                         timer-width = <32>;
 884                         power-domains = <&pd_ttc0>;
 885                 };
 886
 887                 ttc1: timer@ff120000 {
 888                         compatible = "cdns,ttc";
 889                         status = "disabled";
 890                         interrupt-parent = <&gic>;
 891                         interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
 892                         reg = <0x0 0xff120000 0x0 0x1000>;
 893                         timer-width = <32>;
 894                         power-domains = <&pd_ttc1>;
 895                 };
 896
 897                 ttc2: timer@ff130000 {
 898                         compatible = "cdns,ttc";
 899                         status = "disabled";
 900                         interrupt-parent = <&gic>;
 901                         interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
 902                         reg = <0x0 0xff130000 0x0 0x1000>;
 903                         timer-width = <32>;
 904                         power-domains = <&pd_ttc2>;
 905                 };
 906
 907                 ttc3: timer@ff140000 {
 908                         compatible = "cdns,ttc";
 909                         status = "disabled";
 910                         interrupt-parent = <&gic>;
 911                         interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
 912                         reg = <0x0 0xff140000 0x0 0x1000>;
 913                         timer-width = <32>;
 914                         power-domains = <&pd_ttc3>;
 915                 };
 916
 917                 uart0: serial@ff000000 {
 918                         u-boot,dm-pre-reloc;
 919                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 920                         status = "disabled";
 921                         interrupt-parent = <&gic>;
 922                         interrupts = <0 21 4>;
 923                         reg = <0x0 0xff000000 0x0 0x1000>;
 924                         clock-names = "uart_clk", "pclk";
 925                         power-domains = <&pd_uart0>;
 926                 };
 927
 928                 uart1: serial@ff010000 {
 929                         u-boot,dm-pre-reloc;
 930                         compatible = "cdns,uart-r1p12", "xlnx,xuartps";
 931                         status = "disabled";
 932                         interrupt-parent = <&gic>;
 933                         interrupts = <0 22 4>;
 934                         reg = <0x0 0xff010000 0x0 0x1000>;
 935                         clock-names = "uart_clk", "pclk";
 936                         power-domains = <&pd_uart1>;
 937                 };
 938
 939                 usb0: usb0 {
 940                         #address-cells = <2>;
 941                         #size-cells = <2>;
 942                         status = "disabled";
 943                         compatible = "xlnx,zynqmp-dwc3";
 944                         clock-names = "bus_clk", "ref_clk";
 945                         clocks = <&clk125>, <&clk125>;
 946                         #stream-id-cells = <1>;
 947                         iommus = <&smmu 0x860>;
 948                         power-domains = <&pd_usb0>;
 949                         ranges;
 950
 951                         dwc3_0: dwc3@fe200000 {
 952                                 compatible = "snps,dwc3";
 953                                 status = "disabled";
 954                                 reg = <0x0 0xfe200000 0x0 0x40000>;
 955                                 interrupt-parent = <&gic>;
 956                                 interrupts = <0 65 4>;
 957                                 /* snps,quirk-frame-length-adjustment = <0x20>; */
 958                                 snps,refclk_fladj;
 959                         };
 960                 };
 961
 962                 usb1: usb1 {
 963                         #address-cells = <2>;
 964                         #size-cells = <2>;
 965                         status = "disabled";
 966                         compatible = "xlnx,zynqmp-dwc3";
 967                         clock-names = "bus_clk", "ref_clk";
 968                         clocks = <&clk125>, <&clk125>;
 969                         #stream-id-cells = <1>;
 970                         iommus = <&smmu 0x861>;
 971                         power-domains = <&pd_usb1>;
 972                         ranges;
 973
 974                         dwc3_1: dwc3@fe300000 {
 975                                 compatible = "snps,dwc3";
 976                                 status = "disabled";
 977                                 reg = <0x0 0xfe300000 0x0 0x40000>;
 978                                 interrupt-parent = <&gic>;
 979                                 interrupts = <0 70 4>;
 980                                 /* snps,quirk-frame-length-adjustment = <0x20>; */
 981                                 snps,refclk_fladj;
 982                         };
 983                 };
 984
 985                 watchdog0: watchdog@fd4d0000 {
 986                         compatible = "cdns,wdt-r1p2";
 987                         status = "disabled";
 988                         interrupt-parent = <&gic>;
 989                         interrupts = <0 113 1>;
 990                         reg = <0x0 0xfd4d0000 0x0 0x1000>;
 991                         timeout-sec = <10>;
 992                 };
 993
 994                 xilinx_drm: xilinx_drm {
 995                         compatible = "xlnx,drm";
 996                         status = "disabled";
 997                         xlnx,encoder-slave = <&xlnx_dp>;
 998                         xlnx,connector-type = "DisplayPort";
 999                         xlnx,dp-sub = <&xlnx_dp_sub>;
1000                         planes {
1001                                 xlnx,pixel-format = "rgb565";
1002                                 plane0 {
1003                                         dmas = <&xlnx_dpdma 3>;
1004                                         dma-names = "dma0";
1005                                 };
1006                                 plane1 {
1007                                         dmas = <&xlnx_dpdma 0>,
1008                                                <&xlnx_dpdma 1>,
1009                                                <&xlnx_dpdma 2>;
1010                                         dma-names = "dma0", "dma1", "dma2";
1011                                 };
1012                         };
1013                 };
1014
1015                 xlnx_dp: dp@fd4a0000 {
1016                         compatible = "xlnx,v-dp";
1017                         status = "disabled";
1018                         reg = <0x0 0xfd4a0000 0x0 0x1000>;
1019                         interrupts = <0 119 4>;
1020                         interrupt-parent = <&gic>;
1021                         clock-names = "aclk", "aud_clk";
1022                         power-domains = <&pd_dp>;
1023                         xlnx,dp-version = "v1.2";
1024                         xlnx,max-lanes = <2>;
1025                         xlnx,max-link-rate = <540000>;
1026                         xlnx,max-bpc = <16>;
1027                         xlnx,enable-ycrcb;
1028                         xlnx,colormetry = "rgb";
1029                         xlnx,bpc = <8>;
1030                         xlnx,audio-chan = <2>;
1031                         xlnx,dp-sub = <&xlnx_dp_sub>;
1032                         xlnx,max-pclock-frequency = <300000>;
1033                 };
1034
1035                 xlnx_dp_snd_card: dp_snd_card {
1036                         compatible = "xlnx,dp-snd-card";
1037                         status = "disabled";
1038                         xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>;
1039                         xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>;
1040                 };
1041
1042                 xlnx_dp_snd_codec0: dp_snd_codec0 {
1043                         compatible = "xlnx,dp-snd-codec";
1044                         status = "disabled";
1045                         clock-names = "aud_clk";
1046                 };
1047
1048                 xlnx_dp_snd_pcm0: dp_snd_pcm0 {
1049                         compatible = "xlnx,dp-snd-pcm";
1050                         status = "disabled";
1051                         dmas = <&xlnx_dpdma 4>;
1052                         dma-names = "tx";
1053                 };
1054
1055                 xlnx_dp_snd_pcm1: dp_snd_pcm1 {
1056                         compatible = "xlnx,dp-snd-pcm";
1057                         status = "disabled";
1058                         dmas = <&xlnx_dpdma 5>;
1059                         dma-names = "tx";
1060                 };
1061
1062                 xlnx_dp_sub: dp_sub@fd4aa000 {
1063                         compatible = "xlnx,dp-sub";
1064                         status = "disabled";
1065                         reg = <0x0 0xfd4aa000 0x0 0x1000>,
1066                               <0x0 0xfd4ab000 0x0 0x1000>,
1067                               <0x0 0xfd4ac000 0x0 0x1000>;
1068                         reg-names = "blend", "av_buf", "aud";
1069                         xlnx,output-fmt = "rgb";
1070                         xlnx,vid-fmt = "yuyv";
1071                         xlnx,gfx-fmt = "rgb565";
1072                         power-domains = <&pd_dp>;
1073                 };
1074
1075                 xlnx_dpdma: dma@fd4c0000 {
1076                         compatible = "xlnx,dpdma";
1077                         status = "disabled";
1078                         reg = <0x0 0xfd4c0000 0x0 0x1000>;
1079                         interrupts = <0 122 4>;
1080                         interrupt-parent = <&gic>;
1081                         clock-names = "axi_clk";
1082                         power-domains = <&pd_dp>;
1083                         dma-channels = <6>;
1084                         #dma-cells = <1>;
1085                         dma-video0channel {
1086                                 compatible = "xlnx,video0";
1087                         };
1088                         dma-video1channel {
1089                                 compatible = "xlnx,video1";
1090                         };
1091                         dma-video2channel {
1092                                 compatible = "xlnx,video2";
1093                         };
1094                         dma-graphicschannel {
1095                                 compatible = "xlnx,graphics";
1096                         };
1097                         dma-audio0channel {
1098                                 compatible = "xlnx,audio0";
1099                         };
1100                         dma-audio1channel {
1101                                 compatible = "xlnx,audio1";
1102                         };
1103                 };
1104         };
1105 };