3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/errno.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/crm_regs.h>
19 #include <ipu_pixfmt.h>
21 #ifdef CONFIG_FSL_ESDHC
22 #include <fsl_esdhc.h>
25 char *get_reset_cause(void)
28 struct src *src_regs = (struct src *)SRC_BASE_ADDR;
30 cause = readl(&src_regs->srsr);
31 writel(cause, &src_regs->srsr);
50 return "unknown reset";
54 #if defined(CONFIG_MX53) || defined(CONFIG_MX6)
55 #if defined(CONFIG_MX53)
56 #define MEMCTL_BASE ESDCTL_BASE_ADDR
58 #define MEMCTL_BASE MMDC_P0_BASE_ADDR
60 static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
61 static const unsigned char bank_lookup[] = {3, 2};
63 /* these MMDC registers are common to the IMX53 and IMX6 */
64 struct esd_mmdc_regs {
74 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
75 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7)
76 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3)
77 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
78 #define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
81 * imx_ddr_size - return size in bytes of DRAM according MMDC config
82 * The MMDC MDCTL register holds the number of bits for row, col, and data
83 * width and the MMDC MDMISC register holds the number of banks. Combine
84 * all these bits to determine the meme size the MMDC has been configured for
86 unsigned imx_ddr_size(void)
88 struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
89 unsigned ctl = readl(&mem->ctl);
90 unsigned misc = readl(&mem->misc);
91 int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */
93 bits += ESD_MMDC_CTL_GET_ROW(ctl);
94 bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)];
95 bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)];
96 bits += ESD_MMDC_CTL_GET_WIDTH(ctl);
97 bits += ESD_MMDC_CTL_GET_CS1(ctl);
99 /* The MX6 can do only 3840 MiB of DRAM */
107 #if defined(CONFIG_DISPLAY_CPUINFO)
109 const char *get_imx_type(u32 imxtype)
113 return "6Q"; /* Quad-core version of the mx6 */
115 return "6D"; /* Dual-core version of the mx6 */
117 return "6DL"; /* Dual Lite version of the mx6 */
118 case MXC_CPU_MX6SOLO:
119 return "6SOLO"; /* Solo version of the mx6 */
121 return "6SL"; /* Solo-Lite version of the mx6 */
123 return "6SX"; /* SoloX version of the mx6 */
133 int print_cpuinfo(void)
137 cpurev = get_cpu_rev();
139 printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
140 get_imx_type((cpurev & 0xFF000) >> 12),
141 (cpurev & 0x000F0) >> 4,
142 (cpurev & 0x0000F) >> 0,
143 mxc_get_clock(MXC_ARM_CLK) / 1000000);
144 printf("Reset cause: %s\n", get_reset_cause());
149 int cpu_eth_init(bd_t *bis)
153 #if defined(CONFIG_FEC_MXC)
154 rc = fecmxc_initialize(bis);
160 #ifdef CONFIG_FSL_ESDHC
162 * Initializes on-chip MMC controllers.
163 * to override, implement board_mmc_init()
165 int cpu_mmc_init(bd_t *bis)
167 return fsl_esdhc_mmc_init(bis);
171 u32 get_ahb_clk(void)
173 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
176 reg = __raw_readl(&imx_ccm->cbcdr);
177 reg &= MXC_CCM_CBCDR_AHB_PODF_MASK;
178 ahb_podf = reg >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
180 return get_periph_clk() / (ahb_podf + 1);
183 #if defined(CONFIG_VIDEO_IPUV3)
184 void arch_preboot_os(void)
186 /* disable video before launching O/S */