2 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/system.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/imx-common/hab.h>
16 /* -------- start of HAB API updates ------------*/
18 #define hab_rvt_report_event_p \
20 ((is_cpu_type(MXC_CPU_MX6Q) || \
21 is_cpu_type(MXC_CPU_MX6D)) && \
22 (soc_rev() >= CHIP_REV_1_5)) ? \
23 ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
24 (is_cpu_type(MXC_CPU_MX6DL) && \
25 (soc_rev() >= CHIP_REV_1_2)) ? \
26 ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
27 ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
30 #define hab_rvt_report_status_p \
32 ((is_cpu_type(MXC_CPU_MX6Q) || \
33 is_cpu_type(MXC_CPU_MX6D)) && \
34 (soc_rev() >= CHIP_REV_1_5)) ? \
35 ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
36 (is_cpu_type(MXC_CPU_MX6DL) && \
37 (soc_rev() >= CHIP_REV_1_2)) ? \
38 ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
39 ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
42 #define hab_rvt_authenticate_image_p \
44 ((is_cpu_type(MXC_CPU_MX6Q) || \
45 is_cpu_type(MXC_CPU_MX6D)) && \
46 (soc_rev() >= CHIP_REV_1_5)) ? \
47 ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
48 (is_cpu_type(MXC_CPU_MX6DL) && \
49 (soc_rev() >= CHIP_REV_1_2)) ? \
50 ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
51 ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
54 #define hab_rvt_entry_p \
56 ((is_cpu_type(MXC_CPU_MX6Q) || \
57 is_cpu_type(MXC_CPU_MX6D)) && \
58 (soc_rev() >= CHIP_REV_1_5)) ? \
59 ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
60 (is_cpu_type(MXC_CPU_MX6DL) && \
61 (soc_rev() >= CHIP_REV_1_2)) ? \
62 ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
63 ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
66 #define hab_rvt_exit_p \
68 ((is_cpu_type(MXC_CPU_MX6Q) || \
69 is_cpu_type(MXC_CPU_MX6D)) && \
70 (soc_rev() >= CHIP_REV_1_5)) ? \
71 ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
72 (is_cpu_type(MXC_CPU_MX6DL) && \
73 (soc_rev() >= CHIP_REV_1_2)) ? \
74 ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
75 ((hab_rvt_exit_t *)HAB_RVT_EXIT) \
79 #define ALIGN_SIZE 0x1000
80 #define CSF_PAD_SIZE 0x2000
81 #define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
82 #define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
83 #define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
84 #define IS_HAB_ENABLED_BIT \
85 (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)
88 * +------------+ 0x0 (DDR_UIMAGE_START) -
90 * +------------+ 0x40 |
97 * . | > Stuff to be authenticated ----+
105 * +------------+ Align to ALIGN_SIZE | |
107 * +------------+ + IVT_SIZE - |
109 * | CSF DATA | <---------------------------------------------------------+
115 * +------------+ + CSF_PAD_SIZE
118 #define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
121 uint8_t tag; /* Tag */
122 uint8_t len[2]; /* Length */
123 uint8_t par; /* Version */
124 uint8_t contents[MAX_RECORD_BYTES];/* Record Data */
128 char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
129 "RSN = HAB_ENG_FAIL (0x30)\n",
130 "RSN = HAB_INV_ADDRESS (0x22)\n",
131 "RSN = HAB_INV_ASSERTION (0x0C)\n",
132 "RSN = HAB_INV_CALL (0x28)\n",
133 "RSN = HAB_INV_CERTIFICATE (0x21)\n",
134 "RSN = HAB_INV_COMMAND (0x06)\n",
135 "RSN = HAB_INV_CSF (0x11)\n",
136 "RSN = HAB_INV_DCD (0x27)\n",
137 "RSN = HAB_INV_INDEX (0x0F)\n",
138 "RSN = HAB_INV_IVT (0x05)\n",
139 "RSN = HAB_INV_KEY (0x1D)\n",
140 "RSN = HAB_INV_RETURN (0x1E)\n",
141 "RSN = HAB_INV_SIGNATURE (0x18)\n",
142 "RSN = HAB_INV_SIZE (0x17)\n",
143 "RSN = HAB_MEM_FAIL (0x2E)\n",
144 "RSN = HAB_OVR_COUNT (0x2B)\n",
145 "RSN = HAB_OVR_STORAGE (0x2D)\n",
146 "RSN = HAB_UNS_ALGORITHM (0x12)\n",
147 "RSN = HAB_UNS_COMMAND (0x03)\n",
148 "RSN = HAB_UNS_ENGINE (0x0A)\n",
149 "RSN = HAB_UNS_ITEM (0x24)\n",
150 "RSN = HAB_UNS_KEY (0x1B)\n",
151 "RSN = HAB_UNS_PROTOCOL (0x14)\n",
152 "RSN = HAB_UNS_STATE (0x09)\n",
156 char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
157 "STS = HAB_FAILURE (0x33)\n",
158 "STS = HAB_WARNING (0x69)\n",
162 char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
163 "ENG = HAB_ENG_SCC (0x03)\n",
164 "ENG = HAB_ENG_RTIC (0x05)\n",
165 "ENG = HAB_ENG_SAHARA (0x06)\n",
166 "ENG = HAB_ENG_CSU (0x0A)\n",
167 "ENG = HAB_ENG_SRTC (0x0C)\n",
168 "ENG = HAB_ENG_DCP (0x1B)\n",
169 "ENG = HAB_ENG_CAAM (0x1D)\n",
170 "ENG = HAB_ENG_SNVS (0x1E)\n",
171 "ENG = HAB_ENG_OCOTP (0x21)\n",
172 "ENG = HAB_ENG_DTCP (0x22)\n",
173 "ENG = HAB_ENG_ROM (0x36)\n",
174 "ENG = HAB_ENG_HDCP (0x24)\n",
175 "ENG = HAB_ENG_RTL (0x77)\n",
176 "ENG = HAB_ENG_SW (0xFF)\n",
180 char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
181 "CTX = HAB_CTX_FAB (0xFF)\n",
182 "CTX = HAB_CTX_ENTRY (0xE1)\n",
183 "CTX = HAB_CTX_TARGET (0x33)\n",
184 "CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
185 "CTX = HAB_CTX_DCD (0xDD)\n",
186 "CTX = HAB_CTX_CSF (0xCF)\n",
187 "CTX = HAB_CTX_COMMAND (0xC0)\n",
188 "CTX = HAB_CTX_AUT_DAT (0xDB)\n",
189 "CTX = HAB_CTX_ASSERT (0xA0)\n",
190 "CTX = HAB_CTX_EXIT (0xEE)\n",
194 uint8_t hab_statuses[5] = {
202 uint8_t hab_reasons[26] = {
231 uint8_t hab_contexts[12] = {
236 HAB_CTX_AUTHENTICATE,
246 uint8_t hab_engines[16] = {
265 bool is_hab_enabled(void)
267 struct imx_sec_config_fuse_t *fuse =
268 (struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
272 ret = fuse_read(fuse->bank, fuse->word, ®);
274 puts("\nSecure boot fuse read error\n");
278 return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
281 static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
284 uint8_t element = list[idx];
285 while (element != -1) {
288 element = list[++idx];
293 void process_event_record(uint8_t *event_data, size_t bytes)
295 struct record *rec = (struct record *)event_data;
297 printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
298 printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
299 printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
300 printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
303 void display_event(uint8_t *event_data, size_t bytes)
307 if (!(event_data && bytes > 0))
310 for (i = 0; i < bytes; i++) {
312 printf("\t0x%02x", event_data[i]);
313 else if ((i % 8) == 0)
314 printf("\n\t0x%02x", event_data[i]);
316 printf(" 0x%02x", event_data[i]);
319 process_event_record(event_data, bytes);
322 int get_hab_status(void)
324 uint32_t index = 0; /* Loop index */
325 uint8_t event_data[128]; /* Event data buffer */
326 size_t bytes = sizeof(event_data); /* Event size in bytes */
327 enum hab_config config = 0;
328 enum hab_state state = 0;
329 hab_rvt_report_event_t *hab_rvt_report_event;
330 hab_rvt_report_status_t *hab_rvt_report_status;
332 hab_rvt_report_event = hab_rvt_report_event_p;
333 hab_rvt_report_status = hab_rvt_report_status_p;
335 if (is_hab_enabled())
336 puts("\nSecure boot enabled\n");
338 puts("\nSecure boot disabled\n");
340 /* Check HAB status */
341 if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
342 printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
345 /* Display HAB Error events */
346 while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
347 &bytes) == HAB_SUCCESS) {
349 printf("--------- HAB Event %d -----------------\n",
351 puts("event data:\n");
352 display_event(event_data, bytes);
354 bytes = sizeof(event_data);
358 /* Display message if no HAB events are found */
360 printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
362 puts("No HAB Events Found!\n\n");
367 uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
369 uint32_t load_addr = 0;
371 ptrdiff_t ivt_offset = 0;
374 hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
375 hab_rvt_entry_t *hab_rvt_entry;
376 hab_rvt_exit_t *hab_rvt_exit;
378 hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
379 hab_rvt_entry = hab_rvt_entry_p;
380 hab_rvt_exit = hab_rvt_exit_p;
382 if (is_hab_enabled()) {
383 printf("\nAuthenticate image from DDR location 0x%x...\n",
386 hab_caam_clock_enable(1);
388 if (hab_rvt_entry() == HAB_SUCCESS) {
389 /* If not already aligned, Align to ALIGN_SIZE */
390 ivt_offset = (image_size + ALIGN_SIZE - 1) &
394 bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
396 printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
397 ivt_offset, ddr_start + ivt_offset);
398 puts("Dumping IVT\n");
399 print_buffer(ddr_start + ivt_offset,
400 (void *)(ddr_start + ivt_offset),
403 puts("Dumping CSF Header\n");
404 print_buffer(ddr_start + ivt_offset+IVT_SIZE,
405 (void *)(ddr_start + ivt_offset+IVT_SIZE),
410 puts("\nCalling authenticate_image in ROM\n");
411 printf("\tivt_offset = 0x%x\n", ivt_offset);
412 printf("\tstart = 0x%08lx\n", start);
413 printf("\tbytes = 0x%x\n", bytes);
416 * If the MMU is enabled, we have to notify the ROM
417 * code, or it won't flush the caches when needed.
418 * This is done, by setting the "pu_irom_mmu_enabled"
419 * word to 1. You can find its address by looking in
420 * the ROM map. This is critical for
421 * authenticate_image(). If MMU is enabled, without
422 * setting this bit, authentication will fail and may
425 /* Check MMU enabled */
426 if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
427 if (is_cpu_type(MXC_CPU_MX6Q) ||
428 is_cpu_type(MXC_CPU_MX6D)) {
430 * This won't work on Rev 1.0.0 of
431 * i.MX6Q/D, since their ROM doesn't
432 * do cache flushes. don't think any
433 * exist, so we ignore them.
436 writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
437 } else if (is_cpu_type(MXC_CPU_MX6DL) ||
438 is_cpu_type(MXC_CPU_MX6SOLO)) {
439 writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
440 } else if (is_cpu_type(MXC_CPU_MX6SL)) {
441 writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
445 load_addr = (uint32_t)hab_rvt_authenticate_image(
447 ivt_offset, (void **)&start,
448 (size_t *)&bytes, NULL);
449 if (hab_rvt_exit() != HAB_SUCCESS) {
450 puts("hab exit function fail\n");
454 puts("hab entry function fail\n");
457 hab_caam_clock_enable(0);
461 puts("hab fuse not enabled\n");
464 if ((!is_hab_enabled()) || (load_addr != 0))
470 int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
482 static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
485 ulong addr, ivt_offset;
489 return CMD_RET_USAGE;
491 addr = simple_strtoul(argv[1], NULL, 16);
492 ivt_offset = simple_strtoul(argv[2], NULL, 16);
494 rcode = authenticate_image(addr, ivt_offset);
500 hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
501 "display HAB status",
506 hab_auth_img, 3, 0, do_authenticate_image,
507 "authenticate image via HAB",
509 "addr - image hex address\n"
510 "ivt_offset - hex offset of IVT in the image"