2 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/system.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/sys_proto.h>
14 #include <asm/imx-common/hab.h>
16 /* -------- start of HAB API updates ------------*/
18 #define hab_rvt_report_event_p \
20 (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
21 ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
22 (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
23 ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
24 ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
27 #define hab_rvt_report_status_p \
29 (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
30 ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
31 (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
32 ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
33 ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
36 #define hab_rvt_authenticate_image_p \
38 (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
39 ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
40 (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
41 ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
42 ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
45 #define hab_rvt_entry_p \
47 (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
48 ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
49 (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
50 ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
51 ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
54 #define hab_rvt_exit_p \
56 (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \
57 ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
58 (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \
59 ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
60 ((hab_rvt_exit_t *)HAB_RVT_EXIT) \
64 #define ALIGN_SIZE 0x1000
65 #define CSF_PAD_SIZE 0x2000
66 #define MX6DQ_PU_IROM_MMU_EN_VAR 0x009024a8
67 #define MX6DLS_PU_IROM_MMU_EN_VAR 0x00901dd0
68 #define MX6SL_PU_IROM_MMU_EN_VAR 0x00900a18
69 #define IS_HAB_ENABLED_BIT \
70 (is_soc_type(MXC_SOC_MX7) ? 0x2000000 : 0x2)
73 * +------------+ 0x0 (DDR_UIMAGE_START) -
75 * +------------+ 0x40 |
82 * . | > Stuff to be authenticated ----+
90 * +------------+ Align to ALIGN_SIZE | |
92 * +------------+ + IVT_SIZE - |
94 * | CSF DATA | <---------------------------------------------------------+
100 * +------------+ + CSF_PAD_SIZE
103 #define MAX_RECORD_BYTES (8*1024) /* 4 kbytes */
106 uint8_t tag; /* Tag */
107 uint8_t len[2]; /* Length */
108 uint8_t par; /* Version */
109 uint8_t contents[MAX_RECORD_BYTES];/* Record Data */
113 char *rsn_str[] = {"RSN = HAB_RSN_ANY (0x00)\n",
114 "RSN = HAB_ENG_FAIL (0x30)\n",
115 "RSN = HAB_INV_ADDRESS (0x22)\n",
116 "RSN = HAB_INV_ASSERTION (0x0C)\n",
117 "RSN = HAB_INV_CALL (0x28)\n",
118 "RSN = HAB_INV_CERTIFICATE (0x21)\n",
119 "RSN = HAB_INV_COMMAND (0x06)\n",
120 "RSN = HAB_INV_CSF (0x11)\n",
121 "RSN = HAB_INV_DCD (0x27)\n",
122 "RSN = HAB_INV_INDEX (0x0F)\n",
123 "RSN = HAB_INV_IVT (0x05)\n",
124 "RSN = HAB_INV_KEY (0x1D)\n",
125 "RSN = HAB_INV_RETURN (0x1E)\n",
126 "RSN = HAB_INV_SIGNATURE (0x18)\n",
127 "RSN = HAB_INV_SIZE (0x17)\n",
128 "RSN = HAB_MEM_FAIL (0x2E)\n",
129 "RSN = HAB_OVR_COUNT (0x2B)\n",
130 "RSN = HAB_OVR_STORAGE (0x2D)\n",
131 "RSN = HAB_UNS_ALGORITHM (0x12)\n",
132 "RSN = HAB_UNS_COMMAND (0x03)\n",
133 "RSN = HAB_UNS_ENGINE (0x0A)\n",
134 "RSN = HAB_UNS_ITEM (0x24)\n",
135 "RSN = HAB_UNS_KEY (0x1B)\n",
136 "RSN = HAB_UNS_PROTOCOL (0x14)\n",
137 "RSN = HAB_UNS_STATE (0x09)\n",
141 char *sts_str[] = {"STS = HAB_SUCCESS (0xF0)\n",
142 "STS = HAB_FAILURE (0x33)\n",
143 "STS = HAB_WARNING (0x69)\n",
147 char *eng_str[] = {"ENG = HAB_ENG_ANY (0x00)\n",
148 "ENG = HAB_ENG_SCC (0x03)\n",
149 "ENG = HAB_ENG_RTIC (0x05)\n",
150 "ENG = HAB_ENG_SAHARA (0x06)\n",
151 "ENG = HAB_ENG_CSU (0x0A)\n",
152 "ENG = HAB_ENG_SRTC (0x0C)\n",
153 "ENG = HAB_ENG_DCP (0x1B)\n",
154 "ENG = HAB_ENG_CAAM (0x1D)\n",
155 "ENG = HAB_ENG_SNVS (0x1E)\n",
156 "ENG = HAB_ENG_OCOTP (0x21)\n",
157 "ENG = HAB_ENG_DTCP (0x22)\n",
158 "ENG = HAB_ENG_ROM (0x36)\n",
159 "ENG = HAB_ENG_HDCP (0x24)\n",
160 "ENG = HAB_ENG_RTL (0x77)\n",
161 "ENG = HAB_ENG_SW (0xFF)\n",
165 char *ctx_str[] = {"CTX = HAB_CTX_ANY(0x00)\n",
166 "CTX = HAB_CTX_FAB (0xFF)\n",
167 "CTX = HAB_CTX_ENTRY (0xE1)\n",
168 "CTX = HAB_CTX_TARGET (0x33)\n",
169 "CTX = HAB_CTX_AUTHENTICATE (0x0A)\n",
170 "CTX = HAB_CTX_DCD (0xDD)\n",
171 "CTX = HAB_CTX_CSF (0xCF)\n",
172 "CTX = HAB_CTX_COMMAND (0xC0)\n",
173 "CTX = HAB_CTX_AUT_DAT (0xDB)\n",
174 "CTX = HAB_CTX_ASSERT (0xA0)\n",
175 "CTX = HAB_CTX_EXIT (0xEE)\n",
179 uint8_t hab_statuses[5] = {
187 uint8_t hab_reasons[26] = {
216 uint8_t hab_contexts[12] = {
221 HAB_CTX_AUTHENTICATE,
231 uint8_t hab_engines[16] = {
250 bool is_hab_enabled(void)
252 struct imx_sec_config_fuse_t *fuse =
253 (struct imx_sec_config_fuse_t *)&imx_sec_config_fuse;
257 ret = fuse_read(fuse->bank, fuse->word, ®);
259 puts("\nSecure boot fuse read error\n");
263 return (reg & IS_HAB_ENABLED_BIT) == IS_HAB_ENABLED_BIT;
266 static inline uint8_t get_idx(uint8_t *list, uint8_t tgt)
269 uint8_t element = list[idx];
270 while (element != -1) {
273 element = list[++idx];
278 void process_event_record(uint8_t *event_data, size_t bytes)
280 struct record *rec = (struct record *)event_data;
282 printf("\n\n%s", sts_str[get_idx(hab_statuses, rec->contents[0])]);
283 printf("%s", rsn_str[get_idx(hab_reasons, rec->contents[1])]);
284 printf("%s", ctx_str[get_idx(hab_contexts, rec->contents[2])]);
285 printf("%s", eng_str[get_idx(hab_engines, rec->contents[3])]);
288 void display_event(uint8_t *event_data, size_t bytes)
292 if (!(event_data && bytes > 0))
295 for (i = 0; i < bytes; i++) {
297 printf("\t0x%02x", event_data[i]);
298 else if ((i % 8) == 0)
299 printf("\n\t0x%02x", event_data[i]);
301 printf(" 0x%02x", event_data[i]);
304 process_event_record(event_data, bytes);
307 int get_hab_status(void)
309 uint32_t index = 0; /* Loop index */
310 uint8_t event_data[128]; /* Event data buffer */
311 size_t bytes = sizeof(event_data); /* Event size in bytes */
312 enum hab_config config = 0;
313 enum hab_state state = 0;
314 hab_rvt_report_event_t *hab_rvt_report_event;
315 hab_rvt_report_status_t *hab_rvt_report_status;
317 hab_rvt_report_event = hab_rvt_report_event_p;
318 hab_rvt_report_status = hab_rvt_report_status_p;
320 if (is_hab_enabled())
321 puts("\nSecure boot enabled\n");
323 puts("\nSecure boot disabled\n");
325 /* Check HAB status */
326 if (hab_rvt_report_status(&config, &state) != HAB_SUCCESS) {
327 printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
330 /* Display HAB Error events */
331 while (hab_rvt_report_event(HAB_FAILURE, index, event_data,
332 &bytes) == HAB_SUCCESS) {
334 printf("--------- HAB Event %d -----------------\n",
336 puts("event data:\n");
337 display_event(event_data, bytes);
339 bytes = sizeof(event_data);
343 /* Display message if no HAB events are found */
345 printf("\nHAB Configuration: 0x%02x, HAB State: 0x%02x\n",
347 puts("No HAB Events Found!\n\n");
352 uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size)
354 uint32_t load_addr = 0;
356 ptrdiff_t ivt_offset = 0;
359 hab_rvt_authenticate_image_t *hab_rvt_authenticate_image;
360 hab_rvt_entry_t *hab_rvt_entry;
361 hab_rvt_exit_t *hab_rvt_exit;
363 hab_rvt_authenticate_image = hab_rvt_authenticate_image_p;
364 hab_rvt_entry = hab_rvt_entry_p;
365 hab_rvt_exit = hab_rvt_exit_p;
367 if (is_hab_enabled()) {
368 printf("\nAuthenticate image from DDR location 0x%x...\n",
371 hab_caam_clock_enable(1);
373 if (hab_rvt_entry() == HAB_SUCCESS) {
374 /* If not already aligned, Align to ALIGN_SIZE */
375 ivt_offset = (image_size + ALIGN_SIZE - 1) &
379 bytes = ivt_offset + IVT_SIZE + CSF_PAD_SIZE;
381 printf("\nivt_offset = 0x%x, ivt addr = 0x%x\n",
382 ivt_offset, ddr_start + ivt_offset);
383 puts("Dumping IVT\n");
384 print_buffer(ddr_start + ivt_offset,
385 (void *)(ddr_start + ivt_offset),
388 puts("Dumping CSF Header\n");
389 print_buffer(ddr_start + ivt_offset+IVT_SIZE,
390 (void *)(ddr_start + ivt_offset+IVT_SIZE),
395 puts("\nCalling authenticate_image in ROM\n");
396 printf("\tivt_offset = 0x%x\n", ivt_offset);
397 printf("\tstart = 0x%08lx\n", start);
398 printf("\tbytes = 0x%x\n", bytes);
401 * If the MMU is enabled, we have to notify the ROM
402 * code, or it won't flush the caches when needed.
403 * This is done, by setting the "pu_irom_mmu_enabled"
404 * word to 1. You can find its address by looking in
405 * the ROM map. This is critical for
406 * authenticate_image(). If MMU is enabled, without
407 * setting this bit, authentication will fail and may
410 /* Check MMU enabled */
411 if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) {
414 * This won't work on Rev 1.0.0 of
415 * i.MX6Q/D, since their ROM doesn't
416 * do cache flushes. don't think any
417 * exist, so we ignore them.
420 writel(1, MX6DQ_PU_IROM_MMU_EN_VAR);
421 } else if (is_mx6sdl()) {
422 writel(1, MX6DLS_PU_IROM_MMU_EN_VAR);
423 } else if (is_mx6sl()) {
424 writel(1, MX6SL_PU_IROM_MMU_EN_VAR);
428 load_addr = (uint32_t)hab_rvt_authenticate_image(
430 ivt_offset, (void **)&start,
431 (size_t *)&bytes, NULL);
432 if (hab_rvt_exit() != HAB_SUCCESS) {
433 puts("hab exit function fail\n");
437 puts("hab entry function fail\n");
440 hab_caam_clock_enable(0);
444 puts("hab fuse not enabled\n");
447 if ((!is_hab_enabled()) || (load_addr != 0))
453 int do_hab_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
465 static int do_authenticate_image(cmd_tbl_t *cmdtp, int flag, int argc,
468 ulong addr, ivt_offset;
472 return CMD_RET_USAGE;
474 addr = simple_strtoul(argv[1], NULL, 16);
475 ivt_offset = simple_strtoul(argv[2], NULL, 16);
477 rcode = authenticate_image(addr, ivt_offset);
483 hab_status, CONFIG_SYS_MAXARGS, 1, do_hab_status,
484 "display HAB status",
489 hab_auth_img, 3, 0, do_authenticate_image,
490 "authenticate image via HAB",
492 "addr - image hex address\n"
493 "ivt_offset - hex offset of IVT in the image"