2 * Based on the iomux-v3.c from Linux kernel:
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
7 * Copyright (C) 2004-2011 Freescale Semiconductor, Inc.
9 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
14 #if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
15 #include <asm/arch/sys_proto.h>
17 #include <asm/imx-common/iomux-v3.h>
19 static void *base = (void *)IOMUXC_BASE_ADDR;
22 * configures a single pad in the iomuxer
24 void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
26 u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
27 u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
29 (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
31 (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
33 (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
34 u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
36 #if defined CONFIG_MX6SL
37 /* Check whether LVE bit needs to be set */
38 if (pad_ctrl & PAD_CTL_LVE) {
39 pad_ctrl &= ~PAD_CTL_LVE;
40 pad_ctrl |= PAD_CTL_LVE_BIT;
44 #ifdef CONFIG_IOMUX_LPSR
45 u32 lpsr = (pad & MUX_MODE_LPSR) >> MUX_MODE_SHIFT;
47 if (lpsr == IOMUX_CONFIG_LPSR) {
48 base = (void *)IOMUXC_LPSR_BASE_ADDR;
49 mux_mode &= ~IOMUX_CONFIG_LPSR;
50 /* set daisy chain sel_input */
52 sel_input_ofs += IOMUX_LPSR_SEL_INPUT_OFS;
56 __raw_writel(mux_mode, base + mux_ctrl_ofs);
59 __raw_writel(sel_input, base + sel_input_ofs);
61 #ifdef CONFIG_IOMUX_SHARE_CONF_REG
62 if (!(pad_ctrl & NO_PAD_CTRL))
63 __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl,
66 if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
67 __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
70 #ifdef CONFIG_IOMUX_LPSR
71 if (lpsr == IOMUX_CONFIG_LPSR)
72 base = (void *)IOMUXC_BASE_ADDR;
77 /* configures a list of pads within declared with IOMUX_PADS macro */
78 void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
81 iomux_v3_cfg_t const *p = pad_list;
85 #if defined(CONFIG_MX6QDL)
87 if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
92 for (i = 0; i < count; i++) {
93 imx_iomux_v3_setup_pad(*p);
98 void imx_iomux_set_gpr_register(int group, int start_bit,
99 int num_bits, int value)
103 reg = readl(base + group * 4);
105 reg &= ~(1<<(start_bit + i));
109 reg |= (value << start_bit);
110 writel(reg, base + group * 4);
113 #ifdef CONFIG_IOMUX_SHARE_CONF_REG
114 void imx_iomux_gpio_set_direction(unsigned int gpio,
115 unsigned int direction)
119 * Only on Vybrid the input/output buffer enable flags
120 * are part of the shared mux/conf register.
122 reg = readl(base + (gpio << 2));
129 writel(reg, base + (gpio << 2));
132 void imx_iomux_gpio_get_function(unsigned int gpio, u32 *gpio_state)
134 *gpio_state = readl(base + (gpio << 2)) &
135 ((0X07 << PAD_MUX_MODE_SHIFT) | PAD_CTL_OBE_IBE_ENABLE);