3 * Sascha Hauer, Pengutronix
5 * (C) Copyright 2009 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/sys_proto.h>
17 /* General purpose timers registers */
20 unsigned int prescaler;
22 unsigned int nouse[6];
26 static struct mxc_gpt *cur_gpt = (struct mxc_gpt *)GPT1_BASE_ADDR;
28 /* General purpose timers bitfields */
29 #define GPTCR_SWR (1 << 15) /* Software reset */
30 #define GPTCR_24MEN (1 << 10) /* Enable 24MHz clock input */
31 #define GPTCR_FRR (1 << 9) /* Freerun / restart */
32 #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source 32khz */
33 #define GPTCR_CLKSOURCE_OSC (5 << 6) /* Clock source OSC */
34 #define GPTCR_CLKSOURCE_PRE (1 << 6) /* Clock source PRECLK */
35 #define GPTCR_CLKSOURCE_MASK (0x7 << 6)
36 #define GPTCR_TEN 1 /* Timer enable */
38 #define GPTPR_PRESCALER24M_SHIFT 12
39 #define GPTPR_PRESCALER24M_MASK (0xF << GPTPR_PRESCALER24M_SHIFT)
41 DECLARE_GLOBAL_DATA_PTR;
43 static inline int gpt_has_clk_source_osc(void)
45 #if defined(CONFIG_MX6)
46 if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
47 (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) ||
48 is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) ||
49 is_cpu_type(MXC_CPU_MX6UL))
58 static inline ulong gpt_get_clk(void)
60 #ifdef CONFIG_MXC_GPT_HCLK
61 if (gpt_has_clk_source_osc())
64 return mxc_get_clock(MXC_IPG_PERCLK);
69 static inline unsigned long long tick_to_time(unsigned long long tick)
71 ulong gpt_clk = gpt_get_clk();
73 tick *= CONFIG_SYS_HZ;
74 do_div(tick, gpt_clk);
79 static inline unsigned long long us_to_tick(unsigned long long usec)
81 ulong gpt_clk = gpt_get_clk();
83 usec = usec * gpt_clk + 999999;
84 do_div(usec, 1000000);
93 /* setup GP Timer 1 */
94 __raw_writel(GPTCR_SWR, &cur_gpt->control);
96 /* We have no udelay by now */
97 for (i = 0; i < 100; i++)
98 __raw_writel(0, &cur_gpt->control);
100 i = __raw_readl(&cur_gpt->control);
101 i &= ~GPTCR_CLKSOURCE_MASK;
103 #ifdef CONFIG_MXC_GPT_HCLK
104 if (gpt_has_clk_source_osc()) {
105 i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
107 /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */
108 if (is_cpu_type(MXC_CPU_MX6DL) ||
109 is_cpu_type(MXC_CPU_MX6SOLO) ||
110 is_cpu_type(MXC_CPU_MX6SX) ||
111 is_cpu_type(MXC_CPU_MX6UL)) {
114 /* Produce 3Mhz clock */
115 __raw_writel((7 << GPTPR_PRESCALER24M_SHIFT),
116 &cur_gpt->prescaler);
119 i |= GPTCR_CLKSOURCE_PRE | GPTCR_TEN;
122 __raw_writel(0, &cur_gpt->prescaler); /* 32Khz */
123 i |= GPTCR_CLKSOURCE_32 | GPTCR_TEN;
125 __raw_writel(i, &cur_gpt->control);
127 gd->arch.tbl = __raw_readl(&cur_gpt->counter);
133 unsigned long long get_ticks(void)
135 ulong now = __raw_readl(&cur_gpt->counter); /* current tick value */
137 /* increment tbu if tbl has rolled over */
138 if (now < gd->arch.tbl)
141 return (((unsigned long long)gd->arch.tbu) << 32) | gd->arch.tbl;
144 ulong get_timer_masked(void)
147 * get_ticks() returns a long long (64 bit), it wraps in
148 * 2^64 / GPT_CLK = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
149 * 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
150 * 5 * 10^6 days - long enough.
152 return tick_to_time(get_ticks());
155 ulong get_timer(ulong base)
157 return get_timer_masked() - base;
160 /* delay x useconds AND preserve advance timstamp value */
161 void __udelay(unsigned long usec)
163 unsigned long long tmp;
166 tmo = us_to_tick(usec);
167 tmp = get_ticks() + tmo; /* get current timestamp */
169 while (get_ticks() < tmp) /* loop till event */
174 * This function is derived from PowerPC code (timebase clock frequency).
175 * On ARM it returns the number of timer ticks per second.
177 ulong get_tbclk(void)
179 return gpt_get_clk();
183 * This function is intended for SHORT delays only.
184 * It will overflow at around 10 seconds @ 400MHz,
185 * or 20 seconds @ 200MHz.
187 unsigned long usec2ticks(unsigned long usec)
192 ticks = ((usec * (get_tbclk()/1000)) + 500) / 1000;
194 ticks = ((usec / 10) * (get_tbclk() / 100000));