6 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
19 #ifndef _CLOCKS_AM33XX_H_
20 #define _CLOCKS_AM33XX_H_
22 #define OSC (V_OSCK/1000000)
24 /* MAIN PLL Fdll = 550 MHz, by default */
25 #ifndef CONFIG_SYS_MPUCLK
26 #define CONFIG_SYS_MPUCLK 550
28 #define MPUPLL_M CONFIG_SYS_MPUCLK
29 #define MPUPLL_N (OSC-1)
32 /* Core PLL Fdll = 1 GHZ, */
33 #define COREPLL_M 1000
34 #define COREPLL_N (OSC-1)
36 #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
37 #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
38 #define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
41 * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
42 * frequency needs to be set to 960 MHZ. Hence,
43 * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
46 #define PERPLL_N (OSC-1)
49 /* DDR Freq is 266 MHZ for now */
50 /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
52 #define DDRPLL_N (OSC-1)
55 extern void pll_init(void);
56 extern void enable_emif_clocks(void);
58 #endif /* endif _CLOCKS_AM33XX_H_ */