4 * AM33xx specific header file
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
14 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
15 #include <asm/types.h>
16 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
18 #include <asm/arch/hardware.h>
20 #define BIT(x) (1 << x)
21 #define CL_BIT(x) (0 << x)
23 /* Timer register bits */
24 #define TCLR_ST BIT(0) /* Start=1 Stop=0 */
25 #define TCLR_AR BIT(1) /* Auto reload */
26 #define TCLR_PRE BIT(5) /* Pre-scaler enable */
27 #define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */
28 #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */
31 #define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
32 #define TST_DEVICE 0x0
33 #define EMU_DEVICE 0x1
37 /* cpu-id for AM33XX and TI81XX family */
40 #define DEVICE_ID (CTRL_BASE + 0x0600)
41 #define DEVICE_ID_MASK 0x1FFF
43 /* MPU max frequencies */
44 #define AM335X_ZCZ_300 0x1FEF
45 #define AM335X_ZCZ_600 0x1FAF
46 #define AM335X_ZCZ_720 0x1F2F
47 #define AM335X_ZCZ_800 0x1E2F
48 #define AM335X_ZCZ_1000 0x1C2F
49 #define AM335X_ZCE_300 0x1FDF
50 #define AM335X_ZCE_600 0x1F9F
52 /* This gives the status of the boot mode pins on the evm */
53 #define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\
56 #define PRM_RSTCTRL_RESET 0x01
57 #define PRM_RSTST_WARM_RESET_MASK 0x232
61 * Using the prescaler, the OMAP watchdog could go for many
62 * months before firing. These limits work without scaling,
63 * with the 60 second default assumed by most tools and docs.
65 #define TIMER_MARGIN_MAX (24 * 60 * 60) /* 1 day */
66 #define TIMER_MARGIN_DEFAULT 60 /* 60 secs */
67 #define TIMER_MARGIN_MIN 1
69 #define PTV 0 /* prescale */
70 #define GET_WLDR_VAL(secs) (0xffffffff - ((secs) * (32768/(1<<PTV))) + 1)
71 #define WDT_WWPS_PEND_WCLR BIT(0)
72 #define WDT_WWPS_PEND_WLDR BIT(2)
73 #define WDT_WWPS_PEND_WTGR BIT(3)
74 #define WDT_WWPS_PEND_WSPR BIT(4)
76 #define WDT_WCLR_PRE BIT(5)
77 #define WDT_WCLR_PTV_OFF 2
79 #ifndef __KERNEL_STRICT_NAMES
84 /* Encapsulating core pll registers */
86 unsigned int wkclkstctrl; /* offset 0x00 */
87 unsigned int wkctrlclkctrl; /* offset 0x04 */
88 unsigned int wkgpio0clkctrl; /* offset 0x08 */
89 unsigned int wkl4wkclkctrl; /* offset 0x0c */
90 unsigned int resv2[4];
91 unsigned int idlestdpllmpu; /* offset 0x20 */
92 unsigned int resv3[2];
93 unsigned int clkseldpllmpu; /* offset 0x2c */
94 unsigned int resv4[1];
95 unsigned int idlestdpllddr; /* offset 0x34 */
96 unsigned int resv5[2];
97 unsigned int clkseldpllddr; /* offset 0x40 */
98 unsigned int resv6[4];
99 unsigned int clkseldplldisp; /* offset 0x54 */
100 unsigned int resv7[1];
101 unsigned int idlestdpllcore; /* offset 0x5c */
102 unsigned int resv8[2];
103 unsigned int clkseldpllcore; /* offset 0x68 */
104 unsigned int resv9[1];
105 unsigned int idlestdpllper; /* offset 0x70 */
106 unsigned int resv10[2];
107 unsigned int clkdcoldodpllper; /* offset 0x7c */
108 unsigned int divm4dpllcore; /* offset 0x80 */
109 unsigned int divm5dpllcore; /* offset 0x84 */
110 unsigned int clkmoddpllmpu; /* offset 0x88 */
111 unsigned int clkmoddpllper; /* offset 0x8c */
112 unsigned int clkmoddpllcore; /* offset 0x90 */
113 unsigned int clkmoddpllddr; /* offset 0x94 */
114 unsigned int clkmoddplldisp; /* offset 0x98 */
115 unsigned int clkseldpllper; /* offset 0x9c */
116 unsigned int divm2dpllddr; /* offset 0xA0 */
117 unsigned int divm2dplldisp; /* offset 0xA4 */
118 unsigned int divm2dpllmpu; /* offset 0xA8 */
119 unsigned int divm2dpllper; /* offset 0xAC */
120 unsigned int resv11[1];
121 unsigned int wkup_uart0ctrl; /* offset 0xB4 */
122 unsigned int wkup_i2c0ctrl; /* offset 0xB8 */
123 unsigned int wkup_adctscctrl; /* offset 0xBC */
124 unsigned int resv12[6];
125 unsigned int divm6dpllcore; /* offset 0xD8 */
129 * Encapsulating peripheral functional clocks
133 unsigned int l4lsclkstctrl; /* offset 0x00 */
134 unsigned int l3sclkstctrl; /* offset 0x04 */
135 unsigned int l4fwclkstctrl; /* offset 0x08 */
136 unsigned int l3clkstctrl; /* offset 0x0c */
138 unsigned int cpgmac0clkctrl; /* offset 0x14 */
139 unsigned int lcdclkctrl; /* offset 0x18 */
140 unsigned int usb0clkctrl; /* offset 0x1C */
142 unsigned int tptc0clkctrl; /* offset 0x24 */
143 unsigned int emifclkctrl; /* offset 0x28 */
144 unsigned int ocmcramclkctrl; /* offset 0x2c */
145 unsigned int gpmcclkctrl; /* offset 0x30 */
146 unsigned int mcasp0clkctrl; /* offset 0x34 */
147 unsigned int uart5clkctrl; /* offset 0x38 */
148 unsigned int mmc0clkctrl; /* offset 0x3C */
149 unsigned int elmclkctrl; /* offset 0x40 */
150 unsigned int i2c2clkctrl; /* offset 0x44 */
151 unsigned int i2c1clkctrl; /* offset 0x48 */
152 unsigned int spi0clkctrl; /* offset 0x4C */
153 unsigned int spi1clkctrl; /* offset 0x50 */
154 unsigned int resv3[3];
155 unsigned int l4lsclkctrl; /* offset 0x60 */
156 unsigned int l4fwclkctrl; /* offset 0x64 */
157 unsigned int mcasp1clkctrl; /* offset 0x68 */
158 unsigned int uart1clkctrl; /* offset 0x6C */
159 unsigned int uart2clkctrl; /* offset 0x70 */
160 unsigned int uart3clkctrl; /* offset 0x74 */
161 unsigned int uart4clkctrl; /* offset 0x78 */
162 unsigned int timer7clkctrl; /* offset 0x7C */
163 unsigned int timer2clkctrl; /* offset 0x80 */
164 unsigned int timer3clkctrl; /* offset 0x84 */
165 unsigned int timer4clkctrl; /* offset 0x88 */
166 unsigned int resv4[8];
167 unsigned int gpio1clkctrl; /* offset 0xAC */
168 unsigned int gpio2clkctrl; /* offset 0xB0 */
169 unsigned int gpio3clkctrl; /* offset 0xB4 */
171 unsigned int tpccclkctrl; /* offset 0xBC */
172 unsigned int dcan0clkctrl; /* offset 0xC0 */
173 unsigned int dcan1clkctrl; /* offset 0xC4 */
175 unsigned int epwmss1clkctrl; /* offset 0xCC */
176 unsigned int emiffwclkctrl; /* offset 0xD0 */
177 unsigned int epwmss0clkctrl; /* offset 0xD4 */
178 unsigned int epwmss2clkctrl; /* offset 0xD8 */
179 unsigned int l3instrclkctrl; /* offset 0xDC */
180 unsigned int l3clkctrl; /* Offset 0xE0 */
181 unsigned int resv8[4];
182 unsigned int mmc1clkctrl; /* offset 0xF4 */
183 unsigned int mmc2clkctrl; /* offset 0xF8 */
184 unsigned int resv9[8];
185 unsigned int l4hsclkstctrl; /* offset 0x11C */
186 unsigned int l4hsclkctrl; /* offset 0x120 */
187 unsigned int resv10[8];
188 unsigned int cpswclkstctrl; /* offset 0x144 */
189 unsigned int lcdcclkstctrl; /* offset 0x148 */
192 /* Encapsulating Display pll registers */
194 unsigned int resv1[2];
195 unsigned int clktimer2clk; /* offset 0x08 */
196 unsigned int resv2[10];
197 unsigned int clklcdcpixelclk; /* offset 0x34 */
200 /* Encapsulating core pll registers */
202 unsigned int resv0[136];
203 unsigned int wkl4wkclkctrl; /* offset 0x220 */
204 unsigned int resv1[55];
205 unsigned int wkclkstctrl; /* offset 0x300 */
206 unsigned int resv2[15];
207 unsigned int wkup_i2c0ctrl; /* offset 0x340 */
209 unsigned int wkup_uart0ctrl; /* offset 0x348 */
210 unsigned int resv4[5];
211 unsigned int wkctrlclkctrl; /* offset 0x360 */
213 unsigned int wkgpio0clkctrl; /* offset 0x368 */
215 unsigned int resv6[109];
216 unsigned int clkmoddpllcore; /* offset 0x520 */
217 unsigned int idlestdpllcore; /* offset 0x524 */
219 unsigned int clkseldpllcore; /* offset 0x52C */
220 unsigned int resv7[2];
221 unsigned int divm4dpllcore; /* offset 0x538 */
222 unsigned int divm5dpllcore; /* offset 0x53C */
223 unsigned int divm6dpllcore; /* offset 0x540 */
225 unsigned int resv8[7];
226 unsigned int clkmoddpllmpu; /* offset 0x560 */
227 unsigned int idlestdpllmpu; /* offset 0x564 */
229 unsigned int clkseldpllmpu; /* offset 0x56c */
230 unsigned int divm2dpllmpu; /* offset 0x570 */
232 unsigned int resv10[11];
233 unsigned int clkmoddpllddr; /* offset 0x5A0 */
234 unsigned int idlestdpllddr; /* offset 0x5A4 */
236 unsigned int clkseldpllddr; /* offset 0x5AC */
237 unsigned int divm2dpllddr; /* offset 0x5B0 */
239 unsigned int resv12[11];
240 unsigned int clkmoddpllper; /* offset 0x5E0 */
241 unsigned int idlestdpllper; /* offset 0x5E4 */
243 unsigned int clkseldpllper; /* offset 0x5EC */
244 unsigned int divm2dpllper; /* offset 0x5F0 */
245 unsigned int resv14[8];
246 unsigned int clkdcoldodpllper; /* offset 0x614 */
248 unsigned int resv15[2];
249 unsigned int clkmoddplldisp; /* offset 0x620 */
250 unsigned int resv16[2];
251 unsigned int clkseldplldisp; /* offset 0x62C */
252 unsigned int divm2dplldisp; /* offset 0x630 */
256 * Encapsulating peripheral functional clocks
260 unsigned int l3clkstctrl; /* offset 0x00 */
261 unsigned int resv0[7];
262 unsigned int l3clkctrl; /* Offset 0x20 */
263 unsigned int resv1[7];
264 unsigned int l3instrclkctrl; /* offset 0x40 */
265 unsigned int resv2[3];
266 unsigned int ocmcramclkctrl; /* offset 0x50 */
267 unsigned int resv3[9];
268 unsigned int tpccclkctrl; /* offset 0x78 */
270 unsigned int tptc0clkctrl; /* offset 0x80 */
272 unsigned int resv5[7];
273 unsigned int l4hsclkctrl; /* offset 0x0A0 */
275 unsigned int l4fwclkctrl; /* offset 0x0A8 */
276 unsigned int resv7[85];
277 unsigned int l3sclkstctrl; /* offset 0x200 */
278 unsigned int resv8[7];
279 unsigned int gpmcclkctrl; /* offset 0x220 */
280 unsigned int resv9[5];
281 unsigned int mcasp0clkctrl; /* offset 0x238 */
283 unsigned int mcasp1clkctrl; /* offset 0x240 */
285 unsigned int mmc2clkctrl; /* offset 0x248 */
286 unsigned int resv12[3];
287 unsigned int qspiclkctrl; /* offset 0x258 */
288 unsigned int resv121;
289 unsigned int usb0clkctrl; /* offset 0x260 */
290 unsigned int resv13[103];
291 unsigned int l4lsclkstctrl; /* offset 0x400 */
292 unsigned int resv14[7];
293 unsigned int l4lsclkctrl; /* offset 0x420 */
295 unsigned int dcan0clkctrl; /* offset 0x428 */
297 unsigned int dcan1clkctrl; /* offset 0x430 */
298 unsigned int resv17[13];
299 unsigned int elmclkctrl; /* offset 0x468 */
301 unsigned int resv18[3];
302 unsigned int gpio1clkctrl; /* offset 0x478 */
304 unsigned int gpio2clkctrl; /* offset 0x480 */
306 unsigned int gpio3clkctrl; /* offset 0x488 */
308 unsigned int gpio4clkctrl; /* offset 0x490 */
310 unsigned int gpio5clkctrl; /* offset 0x498 */
311 unsigned int resv21[3];
313 unsigned int i2c1clkctrl; /* offset 0x4A8 */
315 unsigned int i2c2clkctrl; /* offset 0x4B0 */
316 unsigned int resv23[3];
317 unsigned int mmc0clkctrl; /* offset 0x4C0 */
319 unsigned int mmc1clkctrl; /* offset 0x4C8 */
321 unsigned int resv25[13];
322 unsigned int spi0clkctrl; /* offset 0x500 */
324 unsigned int spi1clkctrl; /* offset 0x508 */
325 unsigned int resv27[9];
326 unsigned int timer2clkctrl; /* offset 0x530 */
328 unsigned int timer3clkctrl; /* offset 0x538 */
330 unsigned int timer4clkctrl; /* offset 0x540 */
331 unsigned int resv30[5];
332 unsigned int timer7clkctrl; /* offset 0x558 */
334 unsigned int resv31[9];
335 unsigned int uart1clkctrl; /* offset 0x580 */
337 unsigned int uart2clkctrl; /* offset 0x588 */
339 unsigned int uart3clkctrl; /* offset 0x590 */
341 unsigned int uart4clkctrl; /* offset 0x598 */
343 unsigned int uart5clkctrl; /* offset 0x5A0 */
344 unsigned int resv36[87];
346 unsigned int emifclkstctrl; /* offset 0x700 */
347 unsigned int resv361[7];
348 unsigned int emifclkctrl; /* offset 0x720 */
349 unsigned int resv37[3];
350 unsigned int emiffwclkctrl; /* offset 0x730 */
351 unsigned int resv371;
352 unsigned int otfaemifclkctrl; /* offset 0x738 */
353 unsigned int resv38[57];
354 unsigned int lcdclkctrl; /* offset 0x820 */
355 unsigned int resv39[183];
356 unsigned int cpswclkstctrl; /* offset 0xB00 */
357 unsigned int resv40[7];
358 unsigned int cpgmac0clkctrl; /* offset 0xB20 */
361 struct cm_device_inst {
362 unsigned int cm_clkout1_ctrl;
363 unsigned int cm_dll_ctrl;
368 unsigned int clktimer2clk; /* offset 0x04 */
370 #endif /* CONFIG_AM43XX */
372 /* Control Module RTC registers */
374 unsigned int rtcclkctrl; /* offset 0x0 */
375 unsigned int clkstctrl; /* offset 0x4 */
378 /* Watchdog timer registers */
380 unsigned int resv1[4];
381 unsigned int wdtwdsc; /* offset 0x010 */
382 unsigned int wdtwdst; /* offset 0x014 */
383 unsigned int wdtwisr; /* offset 0x018 */
384 unsigned int wdtwier; /* offset 0x01C */
385 unsigned int wdtwwer; /* offset 0x020 */
386 unsigned int wdtwclr; /* offset 0x024 */
387 unsigned int wdtwcrr; /* offset 0x028 */
388 unsigned int wdtwldr; /* offset 0x02C */
389 unsigned int wdtwtgr; /* offset 0x030 */
390 unsigned int wdtwwps; /* offset 0x034 */
391 unsigned int resv2[3];
392 unsigned int wdtwdly; /* offset 0x044 */
393 unsigned int wdtwspr; /* offset 0x048 */
394 unsigned int resv3[1];
395 unsigned int wdtwqeoi; /* offset 0x050 */
396 unsigned int wdtwqstar; /* offset 0x054 */
397 unsigned int wdtwqsta; /* offset 0x058 */
398 unsigned int wdtwqens; /* offset 0x05C */
399 unsigned int wdtwqenc; /* offset 0x060 */
400 unsigned int resv4[39];
401 unsigned int wdt_unfr; /* offset 0x100 */
404 /* Timer 32 bit registers */
406 unsigned int tidr; /* offset 0x00 */
407 unsigned char res1[12];
408 unsigned int tiocp_cfg; /* offset 0x10 */
409 unsigned char res2[12];
410 unsigned int tier; /* offset 0x20 */
411 unsigned int tistatr; /* offset 0x24 */
412 unsigned int tistat; /* offset 0x28 */
413 unsigned int tisr; /* offset 0x2c */
414 unsigned int tcicr; /* offset 0x30 */
415 unsigned int twer; /* offset 0x34 */
416 unsigned int tclr; /* offset 0x38 */
417 unsigned int tcrr; /* offset 0x3c */
418 unsigned int tldr; /* offset 0x40 */
419 unsigned int ttgr; /* offset 0x44 */
420 unsigned int twpc; /* offset 0x48 */
421 unsigned int tmar; /* offset 0x4c */
422 unsigned int tcar1; /* offset 0x50 */
423 unsigned int tscir; /* offset 0x54 */
424 unsigned int tcar2; /* offset 0x58 */
429 unsigned int resv1[21];
430 unsigned int uartsyscfg; /* offset 0x54 */
431 unsigned int uartsyssts; /* offset 0x58 */
436 unsigned int vtp0ctrlreg;
439 /* Control Status Register */
441 unsigned int resv1[16];
442 unsigned int statusreg; /* ofset 0x40 */
443 unsigned int resv2[51];
444 unsigned int secure_emif_sdram_config; /* offset 0x0110 */
445 unsigned int resv3[319];
446 unsigned int dev_attr;
449 /* AM33XX GPIO registers */
450 #define OMAP_GPIO_REVISION 0x0000
451 #define OMAP_GPIO_SYSCONFIG 0x0010
452 #define OMAP_GPIO_SYSSTATUS 0x0114
453 #define OMAP_GPIO_IRQSTATUS1 0x002c
454 #define OMAP_GPIO_IRQSTATUS2 0x0030
455 #define OMAP_GPIO_CTRL 0x0130
456 #define OMAP_GPIO_OE 0x0134
457 #define OMAP_GPIO_DATAIN 0x0138
458 #define OMAP_GPIO_DATAOUT 0x013c
459 #define OMAP_GPIO_LEVELDETECT0 0x0140
460 #define OMAP_GPIO_LEVELDETECT1 0x0144
461 #define OMAP_GPIO_RISINGDETECT 0x0148
462 #define OMAP_GPIO_FALLINGDETECT 0x014c
463 #define OMAP_GPIO_DEBOUNCE_EN 0x0150
464 #define OMAP_GPIO_DEBOUNCE_VAL 0x0154
465 #define OMAP_GPIO_CLEARDATAOUT 0x0190
466 #define OMAP_GPIO_SETDATAOUT 0x0194
468 /* Control Device Register */
470 unsigned int deviceid; /* offset 0x00 */
471 unsigned int resv1[7];
472 unsigned int usb_ctrl0; /* offset 0x20 */
474 unsigned int usb_ctrl1; /* offset 0x28 */
476 unsigned int macid0l; /* offset 0x30 */
477 unsigned int macid0h; /* offset 0x34 */
478 unsigned int macid1l; /* offset 0x38 */
479 unsigned int macid1h; /* offset 0x3c */
480 unsigned int resv4[4];
481 unsigned int miisel; /* offset 0x50 */
482 unsigned int resv5[106];
483 unsigned int efuse_sma; /* offset 0x1FC */
486 /* gmii_sel register defines */
487 #define GMII1_SEL_MII 0x0
488 #define GMII1_SEL_RMII 0x1
489 #define GMII1_SEL_RGMII 0x2
490 #define GMII2_SEL_MII 0x0
491 #define GMII2_SEL_RMII 0x4
492 #define GMII2_SEL_RGMII 0x8
493 #define RGMII1_IDMODE BIT(4)
494 #define RGMII2_IDMODE BIT(5)
495 #define RMII1_IO_CLK_EN BIT(6)
496 #define RMII2_IO_CLK_EN BIT(7)
498 #define MII_MODE_ENABLE (GMII1_SEL_MII | GMII2_SEL_MII)
499 #define RMII_MODE_ENABLE (GMII1_SEL_RMII | GMII2_SEL_RMII)
500 #define RGMII_MODE_ENABLE (GMII1_SEL_RGMII | GMII2_SEL_RGMII)
501 #define RGMII_INT_DELAY (RGMII1_IDMODE | RGMII2_IDMODE)
502 #define RMII_CHIPCKL_ENABLE (RMII1_IO_CLK_EN | RMII2_IO_CLK_EN)
507 unsigned int sysconfig;
508 unsigned int clkconfig;
509 unsigned int clkstatus;
511 #define ECAP_CLK_EN BIT(0)
512 #define ECAP_CLK_STOP_REQ BIT(1)
514 struct pwmss_ecap_regs {
521 unsigned int resv1[4];
522 unsigned short ecctl1;
523 unsigned short ecctl2;
526 /* Capture Control register 2 */
527 #define ECTRL2_SYNCOSEL_MASK (0x03 << 6)
528 #define ECTRL2_MDSL_ECAP BIT(9)
529 #define ECTRL2_CTRSTP_FREERUN BIT(4)
530 #define ECTRL2_PLSL_LOW BIT(10)
531 #define ECTRL2_SYNC_EN BIT(5)
533 #endif /* __ASSEMBLY__ */
534 #endif /* __KERNEL_STRICT_NAMES */
536 #endif /* _AM33XX_CPU_H */