6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
22 #include <asm/arch/hardware.h>
25 /* AM335X EMIF Register values */
26 #define VTP_CTRL_READY (0x1 << 5)
27 #define VTP_CTRL_ENABLE (0x1 << 6)
28 #define VTP_CTRL_START_EN (0x1)
29 #define CMD_FORCE 0x00
30 #define CMD_DELAY 0x00
31 #define PHY_DLL_LOCK_DIFF 0x0
32 #define DDR_CKE_CTRL_NORMAL 0x1
34 #define DDR2_EMIF_READ_LATENCY 0x100005 /* Enable Dynamic Power Down */
35 #define DDR2_EMIF_TIM1 0x0666B3C9
36 #define DDR2_EMIF_TIM2 0x243631CA
37 #define DDR2_EMIF_TIM3 0x0000033F
38 #define DDR2_EMIF_SDCFG 0x41805332
39 #define DDR2_EMIF_SDREF 0x0000081a
40 #define DDR2_DLL_LOCK_DIFF 0x0
41 #define DDR2_RATIO 0x80
42 #define DDR2_INVERT_CLKOUT 0x00
43 #define DDR2_RD_DQS 0x12
44 #define DDR2_WR_DQS 0x00
45 #define DDR2_PHY_WRLVL 0x00
46 #define DDR2_PHY_GATELVL 0x00
47 #define DDR2_PHY_WR_DATA 0x40
48 #define DDR2_PHY_FIFO_WE 0x80
49 #define DDR2_PHY_RANK0_DELAY 0x1
50 #define DDR2_IOCTRL_VALUE 0x18B
55 void config_sdram(const struct emif_regs *regs);
60 void set_sdram_timings(const struct emif_regs *regs);
65 void config_ddr_phy(const struct emif_regs *regs);
68 * This structure represents the DDR registers on AM33XX devices.
71 unsigned int resv0[7];
72 unsigned int cm0csratio; /* offset 0x01C */
73 unsigned int cm0csforce; /* offset 0x020 */
74 unsigned int cm0csdelay; /* offset 0x024 */
75 unsigned int cm0dldiff; /* offset 0x028 */
76 unsigned int cm0iclkout; /* offset 0x02C */
77 unsigned int resv1[8];
78 unsigned int cm1csratio; /* offset 0x050 */
79 unsigned int cm1csforce; /* offset 0x054 */
80 unsigned int cm1csdelay; /* offset 0x058 */
81 unsigned int cm1dldiff; /* offset 0x05C */
82 unsigned int cm1iclkout; /* offset 0x060 */
83 unsigned int resv2[8];
84 unsigned int cm2csratio; /* offset 0x084 */
85 unsigned int cm2csforce; /* offset 0x088 */
86 unsigned int cm2csdelay; /* offset 0x08C */
87 unsigned int cm2dldiff; /* offset 0x090 */
88 unsigned int cm2iclkout; /* offset 0x094 */
89 unsigned int resv3[12];
90 unsigned int dt0rdsratio0; /* offset 0x0C8 */
91 unsigned int resv4[4];
92 unsigned int dt0wdsratio0; /* offset 0x0DC */
93 unsigned int resv5[4];
94 unsigned int dt0wiratio0; /* offset 0x0F0 */
96 unsigned int dt0giratio0; /* offset 0x0FC */
97 unsigned int resv7[2];
98 unsigned int dt0fwsratio0; /* offset 0x108 */
99 unsigned int resv8[5];
100 unsigned int dt0wrsratio0; /* offset 0x120 */
101 unsigned int resv9[4];
102 unsigned int dt0rdelays0; /* offset 0x134 */
103 unsigned int dt0dldiff0; /* offset 0x138 */
104 unsigned int resv10[39];
105 unsigned int dt1rdelays0; /* offset 0x1D8 */
109 * Encapsulates DDR CMD control registers.
112 unsigned long cmd0csratio;
113 unsigned long cmd0csforce;
114 unsigned long cmd0csdelay;
115 unsigned long cmd0dldiff;
116 unsigned long cmd0iclkout;
117 unsigned long cmd1csratio;
118 unsigned long cmd1csforce;
119 unsigned long cmd1csdelay;
120 unsigned long cmd1dldiff;
121 unsigned long cmd1iclkout;
122 unsigned long cmd2csratio;
123 unsigned long cmd2csforce;
124 unsigned long cmd2csdelay;
125 unsigned long cmd2dldiff;
126 unsigned long cmd2iclkout;
130 * Encapsulates DDR DATA registers.
133 unsigned long datardsratio0;
134 unsigned long datawdsratio0;
135 unsigned long datawiratio0;
136 unsigned long datagiratio0;
137 unsigned long datafwsratio0;
138 unsigned long datawrsratio0;
139 unsigned long datadldiff0;
143 * Configure DDR CMD control registers
145 void config_cmd_ctrl(const struct cmd_control *cmd);
148 * Configure DDR DATA registers
150 void config_ddr_data(int data_macrono, const struct ddr_data *data);
153 * This structure represents the DDR io control on AM33XX devices.
155 struct ddr_cmdtctrl {
156 unsigned int resv1[1];
157 unsigned int cm0ioctl;
158 unsigned int cm1ioctl;
159 unsigned int cm2ioctl;
160 unsigned int resv2[12];
161 unsigned int dt0ioctl;
162 unsigned int dt1ioctl;
166 * Configure DDR io control registers
168 void config_io_ctrl(unsigned long val);
171 unsigned int ddrioctrl;
172 unsigned int resv1[325];
173 unsigned int ddrckectrl;
176 void config_ddr(short ddr_type);
178 #endif /* _DDR_DEFS_H */