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   1 /*
   2  * hardware.h
   3  *
   4  * hardware specific header
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __AM33XX_HARDWARE_H
  12 #define __AM33XX_HARDWARE_H
  13
  14 #include <config.h>
  15 #include <asm/arch/omap.h>
  16 #ifdef CONFIG_AM33XX
  17 #include <asm/arch/hardware_am33xx.h>
  18 #elif defined(CONFIG_TI816X)
  19 #include <asm/arch/hardware_ti816x.h>
  20 #elif defined(CONFIG_TI814X)
  21 #include <asm/arch/hardware_ti814x.h>
  22 #elif defined(CONFIG_AM43XX)
  23 #include <asm/arch/hardware_am43xx.h>
  24 #endif
  25
  26 /*
  27  * Common hardware definitions
  28  */
  29
  30 /* DM Timer base addresses */
  31 #define DM_TIMER0_BASE                  0x4802C000
  32 #define DM_TIMER1_BASE                  0x4802E000
  33 #define DM_TIMER2_BASE                  0x48040000
  34 #define DM_TIMER3_BASE                  0x48042000
  35 #define DM_TIMER4_BASE                  0x48044000
  36 #define DM_TIMER5_BASE                  0x48046000
  37 #define DM_TIMER6_BASE                  0x48048000
  38 #define DM_TIMER7_BASE                  0x4804A000
  39
  40 /* GPIO Base address */
  41 #define GPIO0_BASE                      0x48032000
  42 #define GPIO1_BASE                      0x4804C000
  43
  44 /* BCH Error Location Module */
  45 #define ELM_BASE                        0x48080000
  46
  47 /* EMIF Base address */
  48 #define EMIF4_0_CFG_BASE                0x4C000000
  49 #define EMIF4_1_CFG_BASE                0x4D000000
  50
  51 /* DDR Base address */
  52 #define DDR_CTRL_ADDR                   0x44E10E04
  53 #define DDR_CONTROL_BASE_ADDR           0x44E11404
  54
  55 /* UART */
  56 #if CONFIG_CONS_INDEX == 1
  57 #       define DEFAULT_UART_BASE UART0_BASE
  58 #elif CONFIG_CONS_INDEX == 2
  59 #       define DEFAULT_UART_BASE UART1_BASE
  60 #elif CONFIG_CONS_INDEX == 3
  61 #       define DEFAULT_UART_BASE UART2_BASE
  62 #elif CONFIG_CONS_INDEX == 4
  63 #       define DEFAULT_UART_BASE UART3_BASE
  64 #elif CONFIG_CONS_INDEX == 5
  65 #       define DEFAULT_UART_BASE UART4_BASE
  66 #elif CONFIG_CONS_INDEX == 6
  67 #       define DEFAULT_UART_BASE UART5_BASE
  68 #endif
  69
  70 /* GPMC Base address */
  71 #define GPMC_BASE                       0x50000000
  72
  73 /* CPSW Config space */
  74 #define CPSW_BASE                       0x4A100000
  75
  76 /* Control status register */
  77 #define CTRL_CRYSTAL_FREQ_SRC_MASK              (1 << 31)
  78 #define CTRL_CRYSTAL_FREQ_SRC_SHIFT             31
  79 #define CTRL_CRYSTAL_FREQ_SELECTION_MASK        (0x3 << 29)
  80 #define CTRL_CRYSTAL_FREQ_SELECTION_SHIFT       29
  81 #define CTRL_SYSBOOT_15_14_MASK                 (0x3 << 22)
  82 #define CTRL_SYSBOOT_15_14_SHIFT                22
  83
  84 #define CTRL_CRYSTAL_FREQ_SRC_SYSBOOT           0x0
  85 #define CTRL_CRYSTAL_FREQ_SRC_EFUSE             0x1
  86
  87 #define NUM_CRYSTAL_FREQ                        0x4
  88
  89 int clk_get(int clk);
  90 #endif /* __AM33XX_HARDWARE_H */