4 * AM33xx hardware specific header
6 * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
8 * SPDX-License-Identifier: GPL-2.0+
11 #ifndef __AM33XX_HARDWARE_AM33XX_H
12 #define __AM33XX_HARDWARE_AM33XX_H
14 /* Module base addresses */
16 /* UART Base Address */
17 #define UART0_BASE 0x44E09000
18 #define UART1_BASE 0x48022000
19 #define UART2_BASE 0x48024000
20 #define UART3_BASE 0x481A6000
21 #define UART4_BASE 0x481A8000
22 #define UART5_BASE 0x481AA000
24 /* GPIO Base address */
25 #define GPIO2_BASE 0x481AC000
28 #define WDT_BASE 0x44E35000
30 /* Control Module Base Address */
31 #define CTRL_BASE 0x44E10000
32 #define CTRL_DEVICE_BASE 0x44E10600
34 /* PRCM Base Address */
35 #define PRCM_BASE 0x44E00000
36 #define CM_PER 0x44E00000
37 #define CM_WKUP 0x44E00400
38 #define CM_DPLL 0x44E00500
39 #define CM_RTC 0x44E00800
41 #define PRM_RSTCTRL (PRCM_BASE + 0x0F00)
42 #define PRM_RSTST (PRM_RSTCTRL + 8)
44 /* VTP Base address */
45 #define VTP0_CTRL_ADDR 0x44E10E0C
46 #define VTP1_CTRL_ADDR 0x48140E10
47 #define PRM_DEVICE_INST 0x44E00F00
49 /* DDR Base address */
50 #define DDR_PHY_CMD_ADDR 0x44E12000
51 #define DDR_PHY_DATA_ADDR 0x44E120C8
52 #define DDR_PHY_CMD_ADDR2 0x47C0C800
53 #define DDR_PHY_DATA_ADDR2 0x47C0C8C8
54 #define DDR_DATA_REGS_NR 2
56 #define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
57 #define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
59 /* CPSW Config space */
60 #define CPSW_MDIO_BASE 0x4A101000
62 /* RTC base address */
63 #define RTC_BASE 0x44E3E000
66 #define USB0_OTG_BASE 0x47401000
67 #define USB1_OTG_BASE 0x47401800
70 #define LCD_CNTL_BASE 0x4830E000
73 #define PWMSS0_BASE 0x48300000
74 #define AM33XX_ECAP0_BASE 0x48300100
75 #define AM33XX_EPWM_BASE 0x48300200
77 #endif /* __AM33XX_HARDWARE_AM33XX_H */