3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * Header file for the Marvell's Feroceon CPU core.
8 * SPDX-License-Identifier: GPL-2.0+
11 #ifndef _ASM_ARCH_ARMADA_XP_H
12 #define _ASM_ARCH_ARMADA_XP_H
14 #define SOC_MV78460_ID 0x7846
16 /* TCLK Core Clock definition */
17 #ifndef CONFIG_SYS_TCLK
18 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
21 /* SOC specific definations */
22 #define INTREG_BASE 0xd0000000
23 #define INTREG_BASE_ADDR_REG (INTREG_BASE + 0x20080)
24 #define SOC_REGS_PHY_BASE 0xf1000000
25 #define MVEBU_REGISTER(x) (SOC_REGS_PHY_BASE + x)
27 #define MVEBU_SDRAM_SCRATCH (MVEBU_REGISTER(0x01504))
28 #define MVEBU_SPI_BASE (MVEBU_REGISTER(0x10600))
29 #define MVEBU_TWSI_BASE (MVEBU_REGISTER(0x11000))
30 #define MVEBU_UART0_BASE (MVEBU_REGISTER(0x12000))
31 #define MVEBU_UART1_BASE (MVEBU_REGISTER(0x12100))
32 #define MVEBU_MPP_BASE (MVEBU_REGISTER(0x18000))
33 #define MVEBU_GPIO0_BASE (MVEBU_REGISTER(0x18100))
34 #define MVEBU_GPIO1_BASE (MVEBU_REGISTER(0x18140))
35 #define MVEBU_GPIO2_BASE (MVEBU_REGISTER(0x18180))
36 #define MVEBU_SYSTEM_REG_BASE (MVEBU_REGISTER(0x18200))
37 #define MVEBU_CPU_WIN_BASE (MVEBU_REGISTER(0x20000))
38 #define MVEBU_SDRAM_BASE (MVEBU_REGISTER(0x20180))
39 #define MVEBU_TIMER_BASE (MVEBU_REGISTER(0x20300))
40 #define MVEBU_EGIGA2_BASE (MVEBU_REGISTER(0x30000))
41 #define MVEBU_EGIGA3_BASE (MVEBU_REGISTER(0x34000))
42 #define MVEBU_REG_PCIE_BASE (MVEBU_REGISTER(0x40000))
43 #define MVEBU_EGIGA0_BASE (MVEBU_REGISTER(0x70000))
44 #define MVEBU_EGIGA1_BASE (MVEBU_REGISTER(0x74000))
46 #define SDRAM_MAX_CS 4
47 #define SDRAM_ADDR_MASK 0xFF000000
49 /* Armada XP GbE controller has 4 ports */
50 #define MAX_MVNETA_DEVS 4
52 /* Kirkwood CPU memory windows */
53 #define MVCPU_WIN_CTRL_DATA CPU_WIN_CTRL_DATA
54 #define MVCPU_WIN_ENABLE CPU_WIN_ENABLE
55 #define MVCPU_WIN_DISABLE CPU_WIN_DISABLE
57 #endif /* _ASM_ARCH_ARMADA_XP_H */