3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _ARMADA100CPU_H
10 #define _ARMADA100CPU_H
13 #include <asm/system.h>
16 * Main Power Management (MPMU) Registers
17 * Refer Datasheet Appendix A.8
19 struct armd1mpmu_registers {
25 u8 pad1[0x030 - 0x014 - 4];
27 u8 pad2[0x200 - 0x030 - 4];
28 u32 wdtpcr; /*0x0200*/
29 u8 pad3[0x1000 - 0x200 - 4];
32 u8 pad4[0x1020 - 0x1004 - 4];
39 * Application Subsystem Power Management
40 * Refer Datasheet Appendix A.9
42 struct armd1apmu_registers {
47 u32 fc_timer; /* 0x010 */
49 u32 ideal_cfg; /* 0x018 */
50 u8 pad3[0x04C - 0x018 - 4];
51 u32 lcdcrc; /* 0x04C */
52 u32 cciccrc; /* 0x050 */
53 u32 sd1crc; /* 0x054 */
54 u32 sd2crc; /* 0x058 */
55 u32 usbcrc; /* 0x05C */
56 u32 nfccrc; /* 0x060 */
57 u32 dmacrc; /* 0x064 */
59 u32 buscrc; /* 0x06C */
60 u8 pad5[0x07C - 0x06C - 4];
61 u32 wake_clr; /* 0x07C */
62 u8 pad6[0x090 - 0x07C - 4];
63 u32 core_status; /* 0x090 */
68 u8 pad7[0x0B0 - 0x0A0 - 4];
71 u8 pad8[0x0C0 - 0x0B4 - 4];
73 u32 pllss; /* 0x0C4 */
75 u32 gccrc; /* 0x0CC */
76 u8 pad9[0x0D4 - 0x0CC - 4];
77 u32 smccrc; /* 0x0D4 */
79 u32 xdcrc; /* 0x0DC */
80 u32 sd3crc; /* 0x0E0 */
81 u32 sd4crc; /* 0x0E4 */
82 u8 pad11[0x0F0 - 0x0E4 - 4];
83 u32 cfcrc; /* 0x0F0 */
84 u32 mspcrc; /* 0x0F4 */
85 u32 cmucrc; /* 0x0F8 */
86 u32 fecrc; /* 0x0FC */
87 u32 pciecrc; /* 0x100 */
88 u32 epdcrc; /* 0x104 */
92 * APB1 Clock Reset/Control Registers
93 * Refer Datasheet Appendix A.10
95 struct armd1apb1_registers {
103 u8 pad0[0x028 - 0x018 - 4];
107 u32 timers; /*0x034*/
108 u8 pad1[0x03c - 0x034 - 4];
110 u32 sw_jtag; /*0x040*/
111 u32 timer1; /*0x044*/
112 u32 onewire; /*0x048*/
113 u8 pad2[0x050 - 0x048 - 4];
114 u32 asfar; /*0x050 AIB Secure First Access Reg*/
115 u32 assar; /*0x054 AIB Secure Second Access Reg*/
116 u8 pad3[0x06c - 0x054 - 4];
119 u8 pad4[0x07c - 0x070 - 4];
120 u32 timer2; /*0x07C*/
121 u8 pad5[0x084 - 0x07c - 4];
126 * APB2 Clock Reset/Control Registers
127 * Refer Datasheet Appendix A.11
129 struct armd1apb2_registers {
130 u32 pad1[0x01C - 0x000];
131 u32 ssp1_clkrst; /* 0x01C */
132 u32 ssp2_clkrst; /* 0x020 */
133 u32 pad2[0x04C - 0x020 - 4];
134 u32 ssp3_clkrst; /* 0x04C */
135 u32 pad3[0x058 - 0x04C - 4];
136 u32 ssp4_clkrst; /* 0x058 */
137 u32 ssp5_clkrst; /* 0x05C */
141 * CPU Interface Registers
142 * Refer Datasheet Appendix A.2
144 struct armd1cpu_registers {
145 u32 chip_id; /* Chip Id Reg */
147 u32 cpu_conf; /* CPU Conf Reg */
149 u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
151 u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
152 u32 mcb_conf; /* MCB Conf Reg */
153 u32 sys_boot_ctl; /* Sytem Boot Control */
159 u32 armd1_sdram_base(int);
160 u32 armd1_sdram_size(int);
162 #endif /* _ARMADA100CPU_H */