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   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2010
   4  * Marvell Semiconductor <www.marvell.com>
   5  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
   6  */
   7
   8 #ifndef _ARMADA100CPU_H
   9 #define _ARMADA100CPU_H
  10
  11 #include <asm/io.h>
  12 #include <asm/system.h>
  13
  14 /*
  15  * Main Power Management (MPMU) Registers
  16  * Refer Datasheet Appendix A.8
  17  */
  18 struct armd1mpmu_registers {
  19         u8 pad0[0x08 - 0x00];
  20         u32 fccr;       /*0x0008*/
  21         u32 pocr;       /*0x000c*/
  22         u32 posr;       /*0x0010*/
  23         u32 succr;      /*0x0014*/
  24         u8 pad1[0x030 - 0x014 - 4];
  25         u32 gpcr;       /*0x0030*/
  26         u8 pad2[0x200 - 0x030 - 4];
  27         u32 wdtpcr;     /*0x0200*/
  28         u8 pad3[0x1000 - 0x200 - 4];
  29         u32 apcr;       /*0x1000*/
  30         u32 apsr;       /*0x1004*/
  31         u8 pad4[0x1020 - 0x1004 - 4];
  32         u32 aprr;       /*0x1020*/
  33         u32 acgr;       /*0x1024*/
  34         u32 arsr;       /*0x1028*/
  35 };
  36
  37 /*
  38  * Application Subsystem Power Management
  39  * Refer Datasheet Appendix A.9
  40  */
  41 struct armd1apmu_registers {
  42         u32 pcr;                /* 0x000 */
  43         u32 ccr;                /* 0x004 */
  44         u32 pad1;
  45         u32 ccsr;               /* 0x00C */
  46         u32 fc_timer;           /* 0x010 */
  47         u32 pad2;
  48         u32 ideal_cfg;          /* 0x018 */
  49         u8 pad3[0x04C - 0x018 - 4];
  50         u32 lcdcrc;             /* 0x04C */
  51         u32 cciccrc;            /* 0x050 */
  52         u32 sd1crc;             /* 0x054 */
  53         u32 sd2crc;             /* 0x058 */
  54         u32 usbcrc;             /* 0x05C */
  55         u32 nfccrc;             /* 0x060 */
  56         u32 dmacrc;             /* 0x064 */
  57         u32 pad4;
  58         u32 buscrc;             /* 0x06C */
  59         u8 pad5[0x07C - 0x06C - 4];
  60         u32 wake_clr;           /* 0x07C */
  61         u8 pad6[0x090 - 0x07C - 4];
  62         u32 core_status;        /* 0x090 */
  63         u32 rfsc;               /* 0x094 */
  64         u32 imr;                /* 0x098 */
  65         u32 irwc;               /* 0x09C */
  66         u32 isr;                /* 0x0A0 */
  67         u8 pad7[0x0B0 - 0x0A0 - 4];
  68         u32 mhst;               /* 0x0B0 */
  69         u32 msr;                /* 0x0B4 */
  70         u8 pad8[0x0C0 - 0x0B4 - 4];
  71         u32 msst;               /* 0x0C0 */
  72         u32 pllss;              /* 0x0C4 */
  73         u32 smb;                /* 0x0C8 */
  74         u32 gccrc;              /* 0x0CC */
  75         u8 pad9[0x0D4 - 0x0CC - 4];
  76         u32 smccrc;             /* 0x0D4 */
  77         u32 pad10;
  78         u32 xdcrc;              /* 0x0DC */
  79         u32 sd3crc;             /* 0x0E0 */
  80         u32 sd4crc;             /* 0x0E4 */
  81         u8 pad11[0x0F0 - 0x0E4 - 4];
  82         u32 cfcrc;              /* 0x0F0 */
  83         u32 mspcrc;             /* 0x0F4 */
  84         u32 cmucrc;             /* 0x0F8 */
  85         u32 fecrc;              /* 0x0FC */
  86         u32 pciecrc;            /* 0x100 */
  87         u32 epdcrc;             /* 0x104 */
  88 };
  89
  90 /*
  91  * APB1 Clock Reset/Control Registers
  92  * Refer Datasheet Appendix A.10
  93  */
  94 struct armd1apb1_registers {
  95         u32 uart1;      /*0x000*/
  96         u32 uart2;      /*0x004*/
  97         u32 gpio;       /*0x008*/
  98         u32 pwm1;       /*0x00c*/
  99         u32 pwm2;       /*0x010*/
 100         u32 pwm3;       /*0x014*/
 101         u32 pwm4;       /*0x018*/
 102         u8 pad0[0x028 - 0x018 - 4];
 103         u32 rtc;        /*0x028*/
 104         u32 twsi0;      /*0x02c*/
 105         u32 kpc;        /*0x030*/
 106         u32 timers;     /*0x034*/
 107         u8 pad1[0x03c - 0x034 - 4];
 108         u32 aib;        /*0x03c*/
 109         u32 sw_jtag;    /*0x040*/
 110         u32 timer1;     /*0x044*/
 111         u32 onewire;    /*0x048*/
 112         u8 pad2[0x050 - 0x048 - 4];
 113         u32 asfar;      /*0x050 AIB Secure First Access Reg*/
 114         u32 assar;      /*0x054 AIB Secure Second Access Reg*/
 115         u8 pad3[0x06c - 0x054 - 4];
 116         u32 twsi1;      /*0x06c*/
 117         u32 uart3;      /*0x070*/
 118         u8 pad4[0x07c - 0x070 - 4];
 119         u32 timer2;     /*0x07C*/
 120         u8 pad5[0x084 - 0x07c - 4];
 121         u32 ac97;       /*0x084*/
 122 };
 123
 124 /*
 125 * APB2 Clock Reset/Control Registers
 126 * Refer Datasheet Appendix A.11
 127 */
 128 struct armd1apb2_registers {
 129         u32 pad1[0x01C - 0x000];
 130         u32 ssp1_clkrst;                /* 0x01C */
 131         u32 ssp2_clkrst;                /* 0x020 */
 132         u32 pad2[0x04C - 0x020 - 4];
 133         u32 ssp3_clkrst;                /* 0x04C */
 134         u32 pad3[0x058 - 0x04C - 4];
 135         u32 ssp4_clkrst;                /* 0x058 */
 136         u32 ssp5_clkrst;                /* 0x05C */
 137 };
 138
 139 /*
 140  * CPU Interface Registers
 141  * Refer Datasheet Appendix A.2
 142  */
 143 struct armd1cpu_registers {
 144         u32 chip_id;            /* Chip Id Reg */
 145         u32 pad;
 146         u32 cpu_conf;           /* CPU Conf Reg */
 147         u32 pad1;
 148         u32 cpu_sram_spd;       /* CPU SRAM Speed Reg */
 149         u32 pad2;
 150         u32 cpu_l2c_spd;        /* CPU L2cache Speed Conf */
 151         u32 mcb_conf;           /* MCB Conf Reg */
 152         u32 sys_boot_ctl;       /* Sytem Boot Control */
 153 };
 154
 155 /*
 156  * Functions
 157  */
 158 u32 armd1_sdram_base(int);
 159 u32 armd1_sdram_size(int);
 160
 161 #endif /* _ARMADA100CPU_H */