1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * eInfochips Ltd. <www.einfochips.com>
5 * Written-by: Ajay Bhargav <contact@8051projects.net>
8 * Marvell Semiconductor <www.marvell.com>
11 #ifndef __UTMI_ARMADA100__
12 #define __UTMI_ARMADA100__
14 #define UTMI_PHY_BASE 0xD4206000
16 /* utmi_ctrl - bits */
17 #define INPKT_DELAY_SOF (1 << 28)
22 #define PLL_FBDIV_MASK 0x00000FF0
24 #define PLL_REFDIV_MASK 0x0000000F
26 #define PLL_READY 0x800000
27 #define VCOCAL_START (1 << 21)
29 #define N_DIVIDER 0xEE
30 #define M_DIVIDER 0x0B
35 #define RCAL_START (1 << 12)
39 * Refer Datasheet Appendix A.21
41 struct armd1usb_phy_reg {
42 u32 utmi_rev; /* USB PHY Revision */
43 u32 utmi_ctrl; /* USB PHY Control register */
44 u32 utmi_pll; /* PLL register */
45 u32 utmi_tx; /* Tx register */
46 u32 utmi_rx; /* Rx register */
47 u32 utmi_ivref; /* IVREF register */
48 u32 utmi_tst_g0; /* Test group 0 register */
49 u32 utmi_tst_g1; /* Test group 1 register */
50 u32 utmi_tst_g2; /* Test group 2 register */
51 u32 utmi_tst_g3; /* Test group 3 register */
52 u32 utmi_tst_g4; /* Test group 4 register */
53 u32 utmi_tst_g5; /* Test group 5 register */
54 u32 utmi_reserve; /* Reserve Register */
55 u32 utmi_usb_int; /* USB interuppt register */
56 u32 utmi_dbg_ctl; /* Debug control register */
57 u32 utmi_otg_addon; /* OTG addon register */
62 #endif /* __UTMI_ARMADA100__ */