2 * Copyright (c) 2016 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_SDRAM_AST2500_H
7 #define _ASM_ARCH_SDRAM_AST2500_H
9 #define SDRAM_UNLOCK_KEY 0xfc600309
10 #define SDRAM_VIDEO_UNLOCK_KEY 0x2003000f
12 #define SDRAM_PCR_CKE_EN (1 << 0)
13 #define SDRAM_PCR_AUTOPWRDN_EN (1 << 1)
14 #define SDRAM_PCR_CKE_DELAY_SHIFT 4
15 #define SDRAM_PCR_CKE_DELAY_MASK 7
16 #define SDRAM_PCR_RESETN_DIS (1 << 7)
17 #define SDRAM_PCR_ODT_EN (1 << 8)
18 #define SDRAM_PCR_ODT_AUTO_ON (1 << 10)
19 #define SDRAM_PCR_ODT_EXT_EN (1 << 11)
20 #define SDRAM_PCR_TCKE_PW_SHIFT 12
21 #define SDRAM_PCR_TCKE_PW_MASK 7
22 #define SDRAM_PCR_RGAP_CTRL_EN (1 << 15)
23 #define SDRAM_PCR_MREQI_DIS (1 << 17)
25 /* Fixed priority DRAM Requests mask */
26 #define SDRAM_REQ_VGA_HW_CURSOR (1 << 0)
27 #define SDRAM_REQ_VGA_TEXT_CG_FONT (1 << 1)
28 #define SDRAM_REQ_VGA_TEXT_ASCII (1 << 2)
29 #define SDRAM_REQ_VGA_CRT (1 << 3)
30 #define SDRAM_REQ_SOC_DC_CURSOR (1 << 4)
31 #define SDRAM_REQ_SOC_DC_OCD (1 << 5)
32 #define SDRAM_REQ_SOC_DC_CRT (1 << 6)
33 #define SDRAM_REQ_VIDEO_HIPRI_WRITE (1 << 7)
34 #define SDRAM_REQ_USB20_EHCI1 (1 << 8)
35 #define SDRAM_REQ_USB20_EHCI2 (1 << 9)
36 #define SDRAM_REQ_CPU (1 << 10)
37 #define SDRAM_REQ_AHB2 (1 << 11)
38 #define SDRAM_REQ_AHB (1 << 12)
39 #define SDRAM_REQ_MAC0 (1 << 13)
40 #define SDRAM_REQ_MAC1 (1 << 14)
41 #define SDRAM_REQ_PCIE (1 << 16)
42 #define SDRAM_REQ_XDMA (1 << 17)
43 #define SDRAM_REQ_ENCRYPTION (1 << 18)
44 #define SDRAM_REQ_VIDEO_FLAG (1 << 21)
45 #define SDRAM_REQ_VIDEO_LOW_PRI_WRITE (1 << 28)
46 #define SDRAM_REQ_2D_RW (1 << 29)
47 #define SDRAM_REQ_MEMCHECK (1 << 30)
49 #define SDRAM_ICR_RESET_ALL (1 << 31)
51 #define SDRAM_CONF_CAP_SHIFT 0
52 #define SDRAM_CONF_CAP_MASK 3
53 #define SDRAM_CONF_DDR4 (1 << 4)
54 #define SDRAM_CONF_SCRAMBLE (1 << 8)
55 #define SDRAM_CONF_SCRAMBLE_PAT2 (1 << 9)
56 #define SDRAM_CONF_CACHE_EN (1 << 10)
57 #define SDRAM_CONF_CACHE_INIT_EN (1 << 12)
58 #define SDRAM_CONF_DUALX8 (1 << 13)
59 #define SDRAM_CONF_CACHE_INIT_DONE (1 << 19)
61 #define SDRAM_CONF_CAP_128M 0
62 #define SDRAM_CONF_CAP_256M 1
63 #define SDRAM_CONF_CAP_512M 2
64 #define SDRAM_CONF_CAP_1024M 3
66 #define SDRAM_MISC_DDR4_TREFRESH (1 << 3)
68 #define SDRAM_PHYCTRL0_INIT (1 << 0)
69 #define SDRAM_PHYCTRL0_AUTO_UPDATE (1 << 1)
70 #define SDRAM_PHYCTRL0_NRST (1 << 2)
72 #define SDRAM_REFRESH_CYCLES_SHIFT 0
73 #define SDRAM_REFRESH_CYCLES_MASK 0xf
74 #define SDRAM_REFRESH_ZQCS_EN (1 << 7)
75 #define SDRAM_REFRESH_PERIOD_SHIFT 8
76 #define SDRAM_REFRESH_PERIOD_MASK 0xf
78 #define SDRAM_TEST_LEN_SHIFT 4
79 #define SDRAM_TEST_LEN_MASK 0xfffff
80 #define SDRAM_TEST_START_ADDR_SHIFT 24
81 #define SDRAM_TEST_START_ADDR_MASK 0x3f
83 #define SDRAM_TEST_EN (1 << 0)
84 #define SDRAM_TEST_MODE_SHIFT 1
85 #define SDRAM_TEST_MODE_MASK 3
86 #define SDRAM_TEST_MODE_WO 0
87 #define SDRAM_TEST_MODE_RB 1
88 #define SDRAM_TEST_MODE_RW 2
89 #define SDRAM_TEST_GEN_MODE_SHIFT 3
90 #define SDRAM_TEST_GEN_MODE_MASK 7
91 #define SDRAM_TEST_TWO_MODES (1 << 6)
92 #define SDRAM_TEST_ERRSTOP (1 << 7)
93 #define SDRAM_TEST_DONE (1 << 12)
94 #define SDRAM_TEST_FAIL (1 << 13)
96 #define SDRAM_AC_TRFC_SHIFT 0
97 #define SDRAM_AC_TRFC_MASK 0xff
101 struct ast2500_sdrammc_regs {
104 u32 gm_protection_key;
108 u32 mr46_mode_setting;
109 u32 mr5_mode_setting;
110 u32 mode_setting_control;
111 u32 mr02_mode_setting;
112 u32 mr13_mode_setting;
115 u32 pri_group_setting;
116 u32 max_grant_len[4];
119 u32 first_ecc_err_addr;
120 u32 last_ecc_err_addr;
124 u32 test_fail_dq_bit;
136 #endif /* __ASSEMBLY__ */
138 #endif /* _ASM_ARCH_SDRAM_AST2500_H */