2 * Copyright (c) 2016 Google, Inc
4 * SPDX-License-Identifier: GPL-2.0+
6 #ifndef _ASM_ARCH_TIMER_H
7 #define _ASM_ARCH_TIMER_H
9 /* Each timer has 4 control bits in ctrl1 register.
10 * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on,
11 * such that timer X uses bits (4 * X - 4):(4 * X - 1)
12 * If the timer does not support PWM, bit 4 is reserved.
14 #define AST_TMC_EN (1 << 0)
15 #define AST_TMC_1MHZ (1 << 1)
16 #define AST_TMC_OVFINTR (1 << 2)
17 #define AST_TMC_PWM (1 << 3)
19 /* Timers are counted from 1 in the datasheet. */
20 #define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1))
22 #define AST_TMC_RATE (1000*1000)
27 * All timers share control registers, which makes it harder to make them
28 * separate devices. Since only one timer is needed at the moment, making
29 * it this just one device.
32 struct ast_timer_counter {
40 struct ast_timer_counter timers1[3];
43 #ifdef CONFIG_ASPEED_AST2500
49 struct ast_timer_counter timers2[5];
52 #endif /* __ASSEMBLY__ */
54 #endif /* _ASM_ARCH_TIMER_H */