git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-at91/at91_tc.h

   1 /*
   2  * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef AT91_TC_H
   8 #define AT91_TC_H
   9
  10 typedef struct at91_tcc {
  11         u32             ccr;    /* 0x00 Channel Control Register */
  12         u32             cmr;    /* 0x04 Channel Mode Register */
  13         u32             reserved1[2];
  14         u32             cv;     /* 0x10 Counter Value */
  15         u32             ra;     /* 0x14 Register A */
  16         u32             rb;     /* 0x18 Register B */
  17         u32             rc;     /* 0x1C Register C */
  18         u32             sr;     /* 0x20 Status Register */
  19         u32             ier;    /* 0x24 Interrupt Enable Register */
  20         u32             idr;    /* 0x28 Interrupt Disable Register */
  21         u32             imr;    /* 0x2C Interrupt Mask Register */
  22         u32             reserved3[4];
  23 } at91_tcc_t;
  24
  25 #define AT91_TC_CCR_CLKEN               0x00000001
  26 #define AT91_TC_CCR_CLKDIS              0x00000002
  27 #define AT91_TC_CCR_SWTRG               0x00000004
  28
  29 #define AT91_TC_CMR_CPCTRG              0x00004000
  30
  31 #define AT91_TC_CMR_TCCLKS_CLOCK1       0x00000000
  32 #define AT91_TC_CMR_TCCLKS_CLOCK2       0x00000001
  33 #define AT91_TC_CMR_TCCLKS_CLOCK3       0x00000002
  34 #define AT91_TC_CMR_TCCLKS_CLOCK4       0x00000003
  35 #define AT91_TC_CMR_TCCLKS_CLOCK5       0x00000004
  36 #define AT91_TC_CMR_TCCLKS_XC0          0x00000005
  37 #define AT91_TC_CMR_TCCLKS_XC1          0x00000006
  38 #define AT91_TC_CMR_TCCLKS_XC2          0x00000007
  39
  40 typedef struct at91_tc {
  41         at91_tcc_t      tc[3];  /* 0x00 TC Channel 0-2 */
  42         u32             bcr;    /* 0xC0 TC Block Control Register */
  43         u32             bmr;    /* 0xC4 TC Block Mode Register */
  44 } at91_tc_t;
  45
  46 #define AT91_TC_BMR_TC0XC0S_TCLK0       0x00000000
  47 #define AT91_TC_BMR_TC0XC0S_NONE        0x00000001
  48 #define AT91_TC_BMR_TC0XC0S_TIOA1       0x00000002
  49 #define AT91_TC_BMR_TC0XC0S_TIOA2       0x00000003
  50
  51 #define AT91_TC_BMR_TC1XC1S_TCLK1       0x00000000
  52 #define AT91_TC_BMR_TC1XC1S_NONE        0x00000004
  53 #define AT91_TC_BMR_TC1XC1S_TIOA0       0x00000008
  54 #define AT91_TC_BMR_TC1XC1S_TIOA2       0x0000000C
  55
  56 #define AT91_TC_BMR_TC2XC2S_TCLK2       0x00000000
  57 #define AT91_TC_BMR_TC2XC2S_NONE        0x00000010
  58 #define AT91_TC_BMR_TC2XC2S_TIOA0       0x00000020
  59 #define AT91_TC_BMR_TC2XC2S_TIOA1       0x00000030
  60
  61 #endif