2 * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_wdt.h]
4 * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 * Copyright (C) 2007 Andrew Victor
6 * Copyright (C) 2007 Atmel Corporation.
8 * SDRAM Controllers (SDRAMC) - System peripherals registers.
9 * Based on AT91SAM9261 datasheet revision D.
11 * SPDX-License-Identifier: GPL-2.0+
14 #ifndef AT91SAM9_SDRAMC_H
15 #define AT91SAM9_SDRAMC_H
19 #ifndef ATMEL_BASE_SDRAMC
20 #define ATMEL_BASE_SDRAMC ATMEL_BASE_SDRAMC0
23 #define AT91_ASM_SDRAMC_MR ATMEL_BASE_SDRAMC
24 #define AT91_ASM_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04)
25 #define AT91_ASM_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08)
26 #define AT91_ASM_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24)
30 /* SDRAM Controller (SDRAMC) registers */
31 #define AT91_SDRAMC_MR (ATMEL_BASE_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
32 #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
33 #define AT91_SDRAMC_MODE_NORMAL 0
34 #define AT91_SDRAMC_MODE_NOP 1
35 #define AT91_SDRAMC_MODE_PRECHARGE 2
36 #define AT91_SDRAMC_MODE_LMR 3
37 #define AT91_SDRAMC_MODE_REFRESH 4
38 #define AT91_SDRAMC_MODE_EXT_LMR 5
39 #define AT91_SDRAMC_MODE_DEEP 6
41 #define AT91_SDRAMC_TR (ATMEL_BASE_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
42 #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
44 #define AT91_SDRAMC_CR (ATMEL_BASE_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
45 #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
46 #define AT91_SDRAMC_NC_8 (0 << 0)
47 #define AT91_SDRAMC_NC_9 (1 << 0)
48 #define AT91_SDRAMC_NC_10 (2 << 0)
49 #define AT91_SDRAMC_NC_11 (3 << 0)
50 #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
51 #define AT91_SDRAMC_NR_11 (0 << 2)
52 #define AT91_SDRAMC_NR_12 (1 << 2)
53 #define AT91_SDRAMC_NR_13 (2 << 2)
54 #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
55 #define AT91_SDRAMC_NB_2 (0 << 4)
56 #define AT91_SDRAMC_NB_4 (1 << 4)
57 #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
58 #define AT91_SDRAMC_CAS_1 (1 << 5)
59 #define AT91_SDRAMC_CAS_2 (2 << 5)
60 #define AT91_SDRAMC_CAS_3 (3 << 5)
61 #define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
62 #define AT91_SDRAMC_DBW_32 (0 << 7)
63 #define AT91_SDRAMC_DBW_16 (1 << 7)
64 #define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
65 #define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
66 #define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
67 #define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
68 #define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
69 #define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
71 #define AT91_SDRAMC_LPR (ATMEL_BASE_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
72 #define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
73 #define AT91_SDRAMC_LPCB_DISABLE 0
74 #define AT91_SDRAMC_LPCB_SELF_REFRESH 1
75 #define AT91_SDRAMC_LPCB_POWER_DOWN 2
76 #define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
77 #define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
78 #define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
79 #define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
80 #define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
81 #define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
82 #define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
83 #define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
85 #define AT91_SDRAMC_IER (ATMEL_BASE_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
86 #define AT91_SDRAMC_IDR (ATMEL_BASE_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
87 #define AT91_SDRAMC_IMR (ATMEL_BASE_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
88 #define AT91_SDRAMC_ISR (ATMEL_BASE_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
89 #define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
91 #define AT91_SDRAMC_MDR (ATMEL_BASE_SDRAMC + 0x24) /* SDRAM Memory Device Register */
92 #define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
93 #define AT91_SDRAMC_MD_SDRAM 0
94 #define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1