2 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
6 * -------------------------------------------------------------------------
8 * linux/include/asm-arm/arch-davinci/hardware.h
10 * Copyright (C) 2006 Texas Instruments.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
33 #ifndef __ASM_ARCH_HARDWARE_H
34 #define __ASM_ARCH_HARDWARE_H
37 #include <asm/sizes.h>
39 #define REG(addr) (*(volatile unsigned int *)(addr))
40 #define REG_P(addr) ((volatile unsigned int *)(addr))
42 typedef volatile unsigned int dv_reg;
43 typedef volatile unsigned int * dv_reg_p;
46 * Base register addresses
48 * NOTE: some of these DM6446-specific addresses DO NOT WORK
49 * on other DaVinci chips. Double check them before you try
50 * using the addresses ... or PSC module identifiers, etc.
52 #ifndef CONFIG_SOC_DA8XX
54 #define DAVINCI_DMA_3PCC_BASE (0x01c00000)
55 #define DAVINCI_DMA_3PTC0_BASE (0x01c10000)
56 #define DAVINCI_DMA_3PTC1_BASE (0x01c10400)
57 #define DAVINCI_UART0_BASE (0x01c20000)
58 #define DAVINCI_UART1_BASE (0x01c20400)
59 #define DAVINCI_TIMER3_BASE (0x01c20800)
60 #define DAVINCI_I2C_BASE (0x01c21000)
61 #define DAVINCI_TIMER0_BASE (0x01c21400)
62 #define DAVINCI_TIMER1_BASE (0x01c21800)
63 #define DAVINCI_WDOG_BASE (0x01c21c00)
64 #define DAVINCI_PWM0_BASE (0x01c22000)
65 #define DAVINCI_PWM1_BASE (0x01c22400)
66 #define DAVINCI_PWM2_BASE (0x01c22800)
67 #define DAVINCI_TIMER4_BASE (0x01c23800)
68 #define DAVINCI_SYSTEM_MODULE_BASE (0x01c40000)
69 #define DAVINCI_PLL_CNTRL0_BASE (0x01c40800)
70 #define DAVINCI_PLL_CNTRL1_BASE (0x01c40c00)
71 #define DAVINCI_PWR_SLEEP_CNTRL_BASE (0x01c41000)
72 #define DAVINCI_ARM_INTC_BASE (0x01c48000)
73 #define DAVINCI_USB_OTG_BASE (0x01c64000)
74 #define DAVINCI_CFC_ATA_BASE (0x01c66000)
75 #define DAVINCI_SPI_BASE (0x01c66800)
76 #define DAVINCI_GPIO_BASE (0x01c67000)
77 #define DAVINCI_VPSS_REGS_BASE (0x01c70000)
78 #if !defined(CONFIG_SOC_DM646X)
79 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000)
80 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000)
81 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000)
82 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000)
84 #define DAVINCI_DDR_BASE (0x80000000)
86 #ifdef CONFIG_SOC_DM644X
87 #define DAVINCI_UART2_BASE 0x01c20800
88 #define DAVINCI_UHPI_BASE 0x01c67800
89 #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01c80000
90 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01c81000
91 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01c82000
92 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01c84000
93 #define DAVINCI_IMCOP_BASE 0x01cc0000
94 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e00000
95 #define DAVINCI_VLYNQ_BASE 0x01e01000
96 #define DAVINCI_ASP_BASE 0x01e02000
97 #define DAVINCI_MMC_SD_BASE 0x01e10000
98 #define DAVINCI_MS_BASE 0x01e20000
99 #define DAVINCI_VLYNQ_REMOTE_BASE 0x0c000000
101 #elif defined(CONFIG_SOC_DM355)
102 #define DAVINCI_MMC_SD1_BASE 0x01e00000
103 #define DAVINCI_ASP0_BASE 0x01e02000
104 #define DAVINCI_ASP1_BASE 0x01e04000
105 #define DAVINCI_UART2_BASE 0x01e06000
106 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01e10000
107 #define DAVINCI_MMC_SD0_BASE 0x01e11000
109 #elif defined(CONFIG_SOC_DM365)
110 #define DAVINCI_MMC_SD1_BASE 0x01d00000
111 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x01d10000
112 #define DAVINCI_MMC_SD0_BASE 0x01d11000
113 #define DAVINCI_DDR_EMIF_CTRL_BASE 0x20000000
114 #define DAVINCI_SPI0_BASE 0x01c66000
115 #define DAVINCI_SPI1_BASE 0x01c66800
117 #elif defined(CONFIG_SOC_DM646X)
118 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x20008000
119 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x42000000
120 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x44000000
121 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x46000000
122 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x48000000
126 #else /* CONFIG_SOC_DA8XX */
128 #define DAVINCI_UART0_BASE 0x01c42000
129 #define DAVINCI_UART1_BASE 0x01d0c000
130 #define DAVINCI_UART2_BASE 0x01d0d000
131 #define DAVINCI_I2C0_BASE 0x01c22000
132 #define DAVINCI_I2C1_BASE 0x01e28000
133 #define DAVINCI_TIMER0_BASE 0x01c20000
134 #define DAVINCI_TIMER1_BASE 0x01c21000
135 #define DAVINCI_WDOG_BASE 0x01c21000
136 #define DAVINCI_RTC_BASE 0x01c23000
137 #define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
138 #define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
139 #define DAVINCI_PSC0_BASE 0x01c10000
140 #define DAVINCI_PSC1_BASE 0x01e27000
141 #define DAVINCI_SPI0_BASE 0x01c41000
142 #define DAVINCI_USB_OTG_BASE 0x01e00000
143 #define DAVINCI_SPI1_BASE (cpu_is_da830() ? \
144 0x01e12000 : 0x01f0e000)
145 #define DAVINCI_GPIO_BASE 0x01e26000
146 #define DAVINCI_EMAC_CNTRL_REGS_BASE 0x01e23000
147 #define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE 0x01e22000
148 #define DAVINCI_EMAC_WRAPPER_RAM_BASE 0x01e20000
149 #define DAVINCI_MDIO_CNTRL_REGS_BASE 0x01e24000
150 #define DAVINCI_SYSCFG1_BASE 0x01e2c000
151 #define DAVINCI_MMC_SD0_BASE 0x01c40000
152 #define DAVINCI_MMC_SD1_BASE 0x01e1b000
153 #define DAVINCI_TIMER2_BASE 0x01f0c000
154 #define DAVINCI_TIMER3_BASE 0x01f0d000
155 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE 0x68000000
156 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x40000000
157 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x60000000
158 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x62000000
159 #define DAVINCI_ASYNC_EMIF_DATA_CE4_BASE 0x64000000
160 #define DAVINCI_ASYNC_EMIF_DATA_CE5_BASE 0x66000000
161 #define DAVINCI_DDR_EMIF_CTRL_BASE 0xb0000000
162 #define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
163 #define DAVINCI_INTC_BASE 0xfffee000
164 #define DAVINCI_BOOTCFG_BASE 0x01c14000
165 #define DAVINCI_LCD_CNTL_BASE 0x01e13000
166 #define DAVINCI_L3CBARAM_BASE 0x80000000
167 #define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
168 #define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
169 #define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44)
170 #define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
172 #define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10)
173 #define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14)
174 #define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18)
175 #define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c)
176 #define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
177 #define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
178 #define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
179 #define GPIO_BANK2_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x44)
180 #define GPIO_BANK6_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x88)
181 #define GPIO_BANK6_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x8c)
182 #define GPIO_BANK6_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x90)
183 #define GPIO_BANK6_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x94)
184 #endif /* CONFIG_SOC_DA8XX */
186 /* Power and Sleep Controller (PSC) Domains */
187 #define DAVINCI_GPSC_ARMDOMAIN 0
188 #define DAVINCI_GPSC_DSPDOMAIN 1
190 #ifndef CONFIG_SOC_DA8XX
192 #define DAVINCI_LPSC_VPSSMSTR 0
193 #define DAVINCI_LPSC_VPSSSLV 1
194 #define DAVINCI_LPSC_TPCC 2
195 #define DAVINCI_LPSC_TPTC0 3
196 #define DAVINCI_LPSC_TPTC1 4
197 #define DAVINCI_LPSC_EMAC 5
198 #define DAVINCI_LPSC_EMAC_WRAPPER 6
199 #define DAVINCI_LPSC_MDIO 7
200 #define DAVINCI_LPSC_IEEE1394 8
201 #define DAVINCI_LPSC_USB 9
202 #define DAVINCI_LPSC_ATA 10
203 #define DAVINCI_LPSC_VLYNQ 11
204 #define DAVINCI_LPSC_UHPI 12
205 #define DAVINCI_LPSC_DDR_EMIF 13
206 #define DAVINCI_LPSC_AEMIF 14
207 #define DAVINCI_LPSC_MMC_SD 15
208 #define DAVINCI_LPSC_MEMSTICK 16
209 #define DAVINCI_LPSC_McBSP 17
210 #define DAVINCI_LPSC_I2C 18
211 #define DAVINCI_LPSC_UART0 19
212 #define DAVINCI_LPSC_UART1 20
213 #define DAVINCI_LPSC_UART2 21
214 #define DAVINCI_LPSC_SPI 22
215 #define DAVINCI_LPSC_PWM0 23
216 #define DAVINCI_LPSC_PWM1 24
217 #define DAVINCI_LPSC_PWM2 25
218 #define DAVINCI_LPSC_GPIO 26
219 #define DAVINCI_LPSC_TIMER0 27
220 #define DAVINCI_LPSC_TIMER1 28
221 #define DAVINCI_LPSC_TIMER2 29
222 #define DAVINCI_LPSC_SYSTEM_SUBSYS 30
223 #define DAVINCI_LPSC_ARM 31
224 #define DAVINCI_LPSC_SCR2 32
225 #define DAVINCI_LPSC_SCR3 33
226 #define DAVINCI_LPSC_SCR4 34
227 #define DAVINCI_LPSC_CROSSBAR 35
228 #define DAVINCI_LPSC_CFG27 36
229 #define DAVINCI_LPSC_CFG3 37
230 #define DAVINCI_LPSC_CFG5 38
231 #define DAVINCI_LPSC_GEM 39
232 #define DAVINCI_LPSC_IMCOP 40
233 #define DAVINCI_LPSC_VPSSMASTER 47
234 #define DAVINCI_LPSC_MJCP 50
235 #define DAVINCI_LPSC_HDVICP 51
237 #define DAVINCI_DM646X_LPSC_EMAC 14
238 #define DAVINCI_DM646X_LPSC_UART0 26
239 #define DAVINCI_DM646X_LPSC_I2C 31
240 #define DAVINCI_DM646X_LPSC_TIMER0 34
242 #else /* CONFIG_SOC_DA8XX */
244 #define DAVINCI_LPSC_TPCC 0
245 #define DAVINCI_LPSC_TPTC0 1
246 #define DAVINCI_LPSC_TPTC1 2
247 #define DAVINCI_LPSC_AEMIF 3
248 #define DAVINCI_LPSC_SPI0 4
249 #define DAVINCI_LPSC_MMC_SD 5
250 #define DAVINCI_LPSC_AINTC 6
251 #define DAVINCI_LPSC_ARM_RAM_ROM 7
252 #define DAVINCI_LPSC_SECCTL_KEYMGR 8
253 #define DAVINCI_LPSC_UART0 9
254 #define DAVINCI_LPSC_SCR0 10
255 #define DAVINCI_LPSC_SCR1 11
256 #define DAVINCI_LPSC_SCR2 12
257 #define DAVINCI_LPSC_DMAX 13
258 #define DAVINCI_LPSC_ARM 14
259 #define DAVINCI_LPSC_GEM 15
261 /* for LPSCs in PSC1, offset from 32 for differentiation */
262 #define DAVINCI_LPSC_PSC1_BASE 32
263 #define DAVINCI_LPSC_USB20 (DAVINCI_LPSC_PSC1_BASE + 1)
264 #define DAVINCI_LPSC_USB11 (DAVINCI_LPSC_PSC1_BASE + 2)
265 #define DAVINCI_LPSC_GPIO (DAVINCI_LPSC_PSC1_BASE + 3)
266 #define DAVINCI_LPSC_UHPI (DAVINCI_LPSC_PSC1_BASE + 4)
267 #define DAVINCI_LPSC_EMAC (DAVINCI_LPSC_PSC1_BASE + 5)
268 #define DAVINCI_LPSC_DDR_EMIF (DAVINCI_LPSC_PSC1_BASE + 6)
269 #define DAVINCI_LPSC_McASP0 (DAVINCI_LPSC_PSC1_BASE + 7)
270 #define DAVINCI_LPSC_SPI1 (DAVINCI_LPSC_PSC1_BASE + 10)
271 #define DAVINCI_LPSC_I2C1 (DAVINCI_LPSC_PSC1_BASE + 11)
272 #define DAVINCI_LPSC_UART1 (DAVINCI_LPSC_PSC1_BASE + 12)
273 #define DAVINCI_LPSC_UART2 (DAVINCI_LPSC_PSC1_BASE + 13)
274 #define DAVINCI_LPSC_LCDC (DAVINCI_LPSC_PSC1_BASE + 16)
275 #define DAVINCI_LPSC_ePWM (DAVINCI_LPSC_PSC1_BASE + 17)
276 #define DAVINCI_LPSC_MMCSD1 (DAVINCI_LPSC_PSC1_BASE + 18)
277 #define DAVINCI_LPSC_eCAP (DAVINCI_LPSC_PSC1_BASE + 20)
278 #define DAVINCI_LPSC_L3_CBA_RAM (DAVINCI_LPSC_PSC1_BASE + 31)
280 /* DA830-specific peripherals */
281 #define DAVINCI_LPSC_McASP1 (DAVINCI_LPSC_PSC1_BASE + 8)
282 #define DAVINCI_LPSC_McASP2 (DAVINCI_LPSC_PSC1_BASE + 9)
283 #define DAVINCI_LPSC_eQEP (DAVINCI_LPSC_PSC1_BASE + 21)
284 #define DAVINCI_LPSC_SCR8 (DAVINCI_LPSC_PSC1_BASE + 24)
285 #define DAVINCI_LPSC_SCR7 (DAVINCI_LPSC_PSC1_BASE + 25)
286 #define DAVINCI_LPSC_SCR12 (DAVINCI_LPSC_PSC1_BASE + 26)
288 /* DA850-specific peripherals */
289 #define DAVINCI_LPSC_TPCC1 (DAVINCI_LPSC_PSC1_BASE + 0)
290 #define DAVINCI_LPSC_SATA (DAVINCI_LPSC_PSC1_BASE + 8)
291 #define DAVINCI_LPSC_VPIF (DAVINCI_LPSC_PSC1_BASE + 9)
292 #define DAVINCI_LPSC_McBSP0 (DAVINCI_LPSC_PSC1_BASE + 14)
293 #define DAVINCI_LPSC_McBSP1 (DAVINCI_LPSC_PSC1_BASE + 15)
294 #define DAVINCI_LPSC_MMC_SD1 (DAVINCI_LPSC_PSC1_BASE + 18)
295 #define DAVINCI_LPSC_uPP (DAVINCI_LPSC_PSC1_BASE + 19)
296 #define DAVINCI_LPSC_TPTC2 (DAVINCI_LPSC_PSC1_BASE + 21)
297 #define DAVINCI_LPSC_SCR_F0 (DAVINCI_LPSC_PSC1_BASE + 24)
298 #define DAVINCI_LPSC_SCR_F1 (DAVINCI_LPSC_PSC1_BASE + 25)
299 #define DAVINCI_LPSC_SCR_F2 (DAVINCI_LPSC_PSC1_BASE + 26)
300 #define DAVINCI_LPSC_SCR_F6 (DAVINCI_LPSC_PSC1_BASE + 27)
301 #define DAVINCI_LPSC_SCR_F7 (DAVINCI_LPSC_PSC1_BASE + 28)
302 #define DAVINCI_LPSC_SCR_F8 (DAVINCI_LPSC_PSC1_BASE + 29)
303 #define DAVINCI_LPSC_BR_F7 (DAVINCI_LPSC_PSC1_BASE + 30)
305 #endif /* CONFIG_SOC_DA8XX */
307 void lpsc_on(unsigned int id);
308 void lpsc_syncreset(unsigned int id);
311 void davinci_enable_uart0(void);
312 void davinci_enable_emac(void);
313 void davinci_enable_i2c(void);
314 void davinci_errata_workarounds(void);
316 #ifndef CONFIG_SOC_DA8XX
318 /* Some PSC defines */
319 #define PSC_CHP_SHRTSW (0x01c40038)
320 #define PSC_GBLCTL (0x01c41010)
321 #define PSC_EPCPR (0x01c41070)
322 #define PSC_EPCCR (0x01c41078)
323 #define PSC_PTCMD (0x01c41120)
324 #define PSC_PTSTAT (0x01c41128)
325 #define PSC_PDSTAT (0x01c41200)
326 #define PSC_PDSTAT1 (0x01c41204)
327 #define PSC_PDCTL (0x01c41300)
328 #define PSC_PDCTL1 (0x01c41304)
330 #define PSC_MDCTL_BASE (0x01c41a00)
331 #define PSC_MDSTAT_BASE (0x01c41800)
333 #define VDD3P3V_PWDN (0x01c40048)
334 #define UART0_PWREMU_MGMT (0x01c20030)
336 #define PSC_SILVER_BULLET (0x01c41a20)
338 #else /* CONFIG_SOC_DA8XX */
340 #define PSC_ENABLE 0x3
341 #define PSC_DISABLE 0x2
342 #define PSC_SYNCRESET 0x1
343 #define PSC_SWRSTDISABLE 0x0
345 #define PSC_PSC0_MODULE_ID_CNT 16
346 #define PSC_PSC1_MODULE_ID_CNT 32
348 struct davinci_psc_regs {
357 dv_reg mdstat[PSC_PSC0_MODULE_ID_CNT];
359 dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT];
362 dv_reg mdstat[PSC_PSC1_MODULE_ID_CNT];
364 dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT];
369 #define davinci_psc0_regs ((struct davinci_psc_regs *)DAVINCI_PSC0_BASE)
370 #define davinci_psc1_regs ((struct davinci_psc_regs *)DAVINCI_PSC1_BASE)
372 #endif /* CONFIG_SOC_DA8XX */
374 #define PSC_MDSTAT_STATE 0x3f
375 #define PSC_MDCTL_NEXT 0x07
377 #ifndef CONFIG_SOC_DA8XX
380 #define VBPR (0x20000020)
382 /* NOTE: system control modules are *highly* chip-specific, both
383 * as to register content (e.g. for muxing) and which registers exist.
385 #define PINMUX0 0x01c40000
386 #define PINMUX1 0x01c40004
387 #define PINMUX2 0x01c40008
388 #define PINMUX3 0x01c4000c
389 #define PINMUX4 0x01c40010
391 struct davinci_uart_ctrl_regs {
398 #define DAVINCI_UART_CTRL_BASE 0x28
400 /* UART PWREMU_MGMT definitions */
401 #define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
402 #define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
403 #define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
405 #else /* CONFIG_SOC_DA8XX */
407 struct davinci_pllc_regs {
440 #define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
441 #define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
442 #define DAVINCI_PLLC_DIV_MASK 0x1f
445 * A clock ID is a 32-bit number where bit 16 represents the PLL controller
446 * (clear is PLLC0, set is PLLC1) and the low 16 bits represent the divisor,
447 * counting from 1. Clock IDs may be passed to clk_get().
450 /* flags to select PLL controller */
451 #define DAVINCI_PLLC0_FLAG (0)
452 #define DAVINCI_PLLC1_FLAG (1 << 16)
454 enum davinci_clk_ids {
456 * Clock IDs for PLL outputs. Each may be switched on/off
457 * independently, and each may map to one or more peripherals.
459 DAVINCI_PLL0_SYSCLK2 = DAVINCI_PLLC0_FLAG | 2,
460 DAVINCI_PLL0_SYSCLK4 = DAVINCI_PLLC0_FLAG | 4,
461 DAVINCI_PLL0_SYSCLK6 = DAVINCI_PLLC0_FLAG | 6,
462 DAVINCI_PLL1_SYSCLK1 = DAVINCI_PLLC1_FLAG | 1,
463 DAVINCI_PLL1_SYSCLK2 = DAVINCI_PLLC1_FLAG | 2,
465 /* map peripherals to clock IDs */
466 DAVINCI_ARM_CLKID = DAVINCI_PLL0_SYSCLK6,
467 DAVINCI_DDR_CLKID = DAVINCI_PLL1_SYSCLK1,
468 DAVINCI_MDIO_CLKID = DAVINCI_PLL0_SYSCLK4,
469 DAVINCI_MMC_CLKID = DAVINCI_PLL0_SYSCLK2,
470 DAVINCI_SPI0_CLKID = DAVINCI_PLL0_SYSCLK2,
471 DAVINCI_MMCSD_CLKID = DAVINCI_PLL0_SYSCLK2,
473 /* special clock ID - output of PLL multiplier */
474 DAVINCI_PLLM_CLKID = 0x0FF,
476 /* special clock ID - output of PLL post divisor */
477 DAVINCI_PLLC_CLKID = 0x100,
479 /* special clock ID - PLL bypass */
480 DAVINCI_AUXCLK_CLKID = 0x101,
483 #define DAVINCI_UART2_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
486 #define DAVINCI_SPI1_CLKID (cpu_is_da830() ? DAVINCI_PLL0_SYSCLK2 \
489 int clk_get(enum davinci_clk_ids id);
492 struct davinci_syscfg_regs {
510 #define davinci_syscfg_regs \
511 ((struct davinci_syscfg_regs *)DAVINCI_BOOTCFG_BASE)
513 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
515 /* Emulation suspend bits */
516 #define DAVINCI_SYSCFG_SUSPSRC_EMAC (1 << 5)
517 #define DAVINCI_SYSCFG_SUSPSRC_I2C (1 << 16)
518 #define DAVINCI_SYSCFG_SUSPSRC_SPI0 (1 << 21)
519 #define DAVINCI_SYSCFG_SUSPSRC_SPI1 (1 << 22)
520 #define DAVINCI_SYSCFG_SUSPSRC_UART0 (1 << 18)
521 #define DAVINCI_SYSCFG_SUSPSRC_UART2 (1 << 20)
522 #define DAVINCI_SYSCFG_SUSPSRC_TIMER0 (1 << 27)
524 struct davinci_syscfg1_regs {
534 #define davinci_syscfg1_regs \
535 ((struct davinci_syscfg1_regs *)DAVINCI_SYSCFG1_BASE)
537 #define DDR_SLEW_CMOSEN_BIT 4
538 #define DDR_SLEW_DDR_PDENA_BIT 5
540 #define VTP_POWERDWN (1 << 6)
541 #define VTP_LOCK (1 << 7)
542 #define VTP_CLKRZ (1 << 13)
543 #define VTP_READY (1 << 15)
544 #define VTP_IOPWRDWN (1 << 14)
546 #define DV_SYSCFG_KICK0_UNLOCK 0x83e70b13
547 #define DV_SYSCFG_KICK1_UNLOCK 0x95a4f1e0
549 /* Interrupt controller */
550 struct davinci_aintc_regs {
563 #define davinci_aintc_regs ((struct davinci_aintc_regs *)DAVINCI_INTC_BASE)
565 struct davinci_uart_ctrl_regs {
572 #define DAVINCI_UART_CTRL_BASE 0x28
573 #define DAVINCI_UART0_CTRL_ADDR (DAVINCI_UART0_BASE + DAVINCI_UART_CTRL_BASE)
574 #define DAVINCI_UART1_CTRL_ADDR (DAVINCI_UART1_BASE + DAVINCI_UART_CTRL_BASE)
575 #define DAVINCI_UART2_CTRL_ADDR (DAVINCI_UART2_BASE + DAVINCI_UART_CTRL_BASE)
577 #define davinci_uart0_ctrl_regs \
578 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART0_CTRL_ADDR)
579 #define davinci_uart1_ctrl_regs \
580 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART1_CTRL_ADDR)
581 #define davinci_uart2_ctrl_regs \
582 ((struct davinci_uart_ctrl_regs *)DAVINCI_UART2_CTRL_ADDR)
584 /* UART PWREMU_MGMT definitions */
585 #define DAVINCI_UART_PWREMU_MGMT_FREE (1 << 0)
586 #define DAVINCI_UART_PWREMU_MGMT_URRST (1 << 13)
587 #define DAVINCI_UART_PWREMU_MGMT_UTRST (1 << 14)
589 static inline int cpu_is_da830(void)
591 unsigned int jtag_id = REG(JTAG_ID_REG);
592 unsigned short part_no = (jtag_id >> 12) & 0xffff;
594 return ((part_no == 0xb7df) ? 1 : 0);
596 static inline int cpu_is_da850(void)
598 unsigned int jtag_id = REG(JTAG_ID_REG);
599 unsigned short part_no = (jtag_id >> 12) & 0xffff;
601 return ((part_no == 0xb7d1) ? 1 : 0);
604 static inline enum davinci_clk_ids get_async3_src(void)
606 return (REG(&davinci_syscfg_regs->cfgchip3) & 0x10) ?
607 DAVINCI_PLL1_SYSCLK2 : DAVINCI_PLL0_SYSCLK2;
610 #endif /* CONFIG_SOC_DA8XX */
612 #if defined(CONFIG_SOC_DM365)
613 #include <asm/arch/aintc_defs.h>
614 #include <asm/arch/ddr2_defs.h>
615 #include <asm/arch/emif_defs.h>
616 #include <asm/arch/gpio.h>
617 #include <asm/arch/pll_defs.h>
618 #include <asm/arch/psc_defs.h>
619 #include <asm/arch/syscfg_defs.h>
620 #include <asm/arch/timer_defs.h>
622 #define TMPBUF 0x00017ff8
623 #define TMPSTATUS 0x00017ff0
624 #define DV_TMPBUF_VAL 0x591b3ed7
625 #define FLAG_PORRST 0x00000001
626 #define FLAG_WDTRST 0x00000002
627 #define FLAG_FLGON 0x00000004
628 #define FLAG_FLGOFF 0x00000010
637 dv_reg month; /* 0x10 */
641 dv_reg alarmsecond; /* 0x20 */
645 dv_reg alarmmonth; /* 0x30 */
648 dv_reg ctrl; /* 0x40 */
652 dv_reg compmsb; /* 0x50 */
655 dv_reg scratch0; /* 0x60 */
659 dv_reg kick1r; /* 0x70 */
662 #define RTC_STATE_BUSY 0x01
663 #define RTC_STATE_RUN 0x02
665 #define RTC_KICK0R_WE 0x83e70b13
666 #define RTC_KICK1R_WE 0x95a4f1e0
668 #define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE)
670 #endif /* __ASM_ARCH_HARDWARE_H */