2 * Davinci MMC Controller Defines - Based on Linux davinci_mmc.c
4 * Copyright (C) 2010 Texas Instruments Incorporated
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #ifndef _SDMMC_DEFS_H_
22 #define _SDMMC_DEFS_H_
24 #include <asm/arch/hardware.h>
26 /* MMC Control Reg fields */
27 #define MMCCTL_DATRST (1 << 0)
28 #define MMCCTL_CMDRST (1 << 1)
29 #define MMCCTL_WIDTH_4_BIT (1 << 2)
30 #define MMCCTL_DATEG_DISABLED (0 << 6)
31 #define MMCCTL_DATEG_RISING (1 << 6)
32 #define MMCCTL_DATEG_FALLING (2 << 6)
33 #define MMCCTL_DATEG_BOTH (3 << 6)
34 #define MMCCTL_PERMDR_LE (0 << 9)
35 #define MMCCTL_PERMDR_BE (1 << 9)
36 #define MMCCTL_PERMDX_LE (0 << 10)
37 #define MMCCTL_PERMDX_BE (1 << 10)
39 /* MMC Clock Control Reg fields */
40 #define MMCCLK_CLKEN (1 << 8)
41 #define MMCCLK_CLKRT_MASK (0xFF << 0)
43 /* MMC Status Reg0 fields */
44 #define MMCST0_DATDNE (1 << 0)
45 #define MMCST0_BSYDNE (1 << 1)
46 #define MMCST0_RSPDNE (1 << 2)
47 #define MMCST0_TOUTRD (1 << 3)
48 #define MMCST0_TOUTRS (1 << 4)
49 #define MMCST0_CRCWR (1 << 5)
50 #define MMCST0_CRCRD (1 << 6)
51 #define MMCST0_CRCRS (1 << 7)
52 #define MMCST0_DXRDY (1 << 9)
53 #define MMCST0_DRRDY (1 << 10)
54 #define MMCST0_DATED (1 << 11)
55 #define MMCST0_TRNDNE (1 << 12)
57 #define MMCST0_ERR_MASK (0x00F8)
59 /* MMC Status Reg1 fields */
60 #define MMCST1_BUSY (1 << 0)
61 #define MMCST1_CLKSTP (1 << 1)
62 #define MMCST1_DXEMP (1 << 2)
63 #define MMCST1_DRFUL (1 << 3)
64 #define MMCST1_DAT3ST (1 << 4)
65 #define MMCST1_FIFOEMP (1 << 5)
66 #define MMCST1_FIFOFUL (1 << 6)
68 /* MMC INT Mask Reg fields */
69 #define MMCIM_EDATDNE (1 << 0)
70 #define MMCIM_EBSYDNE (1 << 1)
71 #define MMCIM_ERSPDNE (1 << 2)
72 #define MMCIM_ETOUTRD (1 << 3)
73 #define MMCIM_ETOUTRS (1 << 4)
74 #define MMCIM_ECRCWR (1 << 5)
75 #define MMCIM_ECRCRD (1 << 6)
76 #define MMCIM_ECRCRS (1 << 7)
77 #define MMCIM_EDXRDY (1 << 9)
78 #define MMCIM_EDRRDY (1 << 10)
79 #define MMCIM_EDATED (1 << 11)
80 #define MMCIM_ETRNDNE (1 << 12)
82 #define MMCIM_MASKALL (0xFFFFFFFF)
84 /* MMC Resp Tout Reg fields */
85 #define MMCTOR_TOR_MASK (0xFF) /* dont write to reg, | it */
86 #define MMCTOR_TOD_20_16_SHIFT (8)
88 /* MMC Data Read Tout Reg fields */
89 #define MMCTOD_TOD_0_15_MASK (0xFFFF)
91 /* MMC Block len Reg fields */
92 #define MMCBLEN_BLEN_MASK (0xFFF)
94 /* MMC Num Blocks Reg fields */
95 #define MMCNBLK_NBLK_MASK (0xFFFF)
96 #define MMCNBLK_NBLK_MAX (0xFFFF)
98 /* MMC Num Blocks Counter Reg fields */
99 #define MMCNBLC_NBLC_MASK (0xFFFF)
101 /* MMC Cmd Reg fields */
102 #define MMCCMD_CMD_MASK (0x3F)
103 #define MMCCMD_PPLEN (1 << 7)
104 #define MMCCMD_BSYEXP (1 << 8)
105 #define MMCCMD_RSPFMT_NONE (0 << 9)
106 #define MMCCMD_RSPFMT_R1567 (1 << 9)
107 #define MMCCMD_RSPFMT_R2 (2 << 9)
108 #define MMCCMD_RSPFMT_R3 (3 << 9)
109 #define MMCCMD_DTRW (1 << 11)
110 #define MMCCMD_STRMTP (1 << 12)
111 #define MMCCMD_WDATX (1 << 13)
112 #define MMCCMD_INITCK (1 << 14)
113 #define MMCCMD_DCLR (1 << 15)
114 #define MMCCMD_DMATRIG (1 << 16)
116 /* FIFO control Reg fields */
117 #define MMCFIFOCTL_FIFORST (1 << 0)
118 #define MMCFIFOCTL_FIFODIR (1 << 1)
119 #define MMCFIFOCTL_FIFOLEV (1 << 2)
120 #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
121 #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
122 #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
123 #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
125 /* Davinci MMC Register definitions */
126 struct davinci_mmc_regs {
159 /* Davinci MMC board definitions */
161 struct davinci_mmc_regs *reg_base; /* Register base address */
162 uint input_clk; /* Input clock to MMC controller */
163 uint host_caps; /* Host capabilities */
164 uint voltages; /* Host supported voltages */
165 uint version; /* MMC Controller version */
169 MMC_CTLR_VERSION_1 = 0, /* DM644x and DM355 */
170 MMC_CTLR_VERSION_2, /* DA830 */
173 int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
175 #endif /* _SDMMC_DEFS_H */