2 * Cirrus Logic EP93xx register definitions.
5 * Matthias Kaehlcke <matthias@kaehlcke.net>
8 * Dominic Rath <Dominic.Rath@gmx.de>
10 * Copyright (C) 2004, 2005
11 * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
13 * Based in large part on linux/include/asm-arm/arch-ep93xx/regmap.h, which is
15 * Copyright (C) 2004 Ray Lehtiniemi
16 * Copyright (C) 2003 Cirrus Logic, Inc
17 * Copyright (C) 1999 ARM Limited.
19 * SPDX-License-Identifier: GPL-2.0+
22 #define EP93XX_AHB_BASE 0x80000000
23 #define EP93XX_APB_BASE 0x80800000
26 * 0x80000000 - 0x8000FFFF: DMA
28 #define DMA_OFFSET 0x000000
29 #define DMA_BASE (EP93XX_AHB_BASE | DMA_OFFSET)
39 uint32_t reserved1[2];
51 struct dma_channel m2p_channel_0;
52 struct dma_channel m2p_channel_1;
53 struct dma_channel m2p_channel_2;
54 struct dma_channel m2p_channel_3;
55 struct dma_channel m2m_channel_0;
56 struct dma_channel m2m_channel_1;
57 struct dma_channel reserved0[2];
58 struct dma_channel m2p_channel_5;
59 struct dma_channel m2p_channel_4;
60 struct dma_channel m2p_channel_7;
61 struct dma_channel m2p_channel_6;
62 struct dma_channel m2p_channel_9;
63 struct dma_channel m2p_channel_8;
64 uint32_t channel_arbitration;
65 uint32_t reserved[15];
66 uint32_t global_interrupt;
71 * 0x80010000 - 0x8001FFFF: Ethernet MAC
73 #define MAC_OFFSET 0x010000
74 #define MAC_BASE (EP93XX_AHB_BASE | MAC_OFFSET)
79 union { /* deal with half-word aligned registers */
102 uint32_t reserved2[2];
112 uint32_t indad_upper;
116 uint32_t reserved3[2];
129 struct mac_queue rxdq;
131 struct mac_queue rxstsq;
133 struct mac_queue txdq;
135 struct mac_queue txstsq;
137 uint32_t rxbufthrshld;
138 uint32_t txbufthrshld;
139 uint32_t rxststhrshld;
140 uint32_t txststhrshld;
148 #define SELFCTL_RWP (1 << 7)
149 #define SELFCTL_GPO0 (1 << 5)
150 #define SELFCTL_PUWE (1 << 4)
151 #define SELFCTL_PDWE (1 << 3)
152 #define SELFCTL_MIIL (1 << 2)
153 #define SELFCTL_RESET (1 << 0)
155 #define INTSTS_RWI (1 << 30)
156 #define INTSTS_RXMI (1 << 29)
157 #define INTSTS_RXBI (1 << 28)
158 #define INTSTS_RXSQI (1 << 27)
159 #define INTSTS_TXLEI (1 << 26)
160 #define INTSTS_ECIE (1 << 25)
161 #define INTSTS_TXUHI (1 << 24)
162 #define INTSTS_MOI (1 << 18)
163 #define INTSTS_TXCOI (1 << 17)
164 #define INTSTS_RXROI (1 << 16)
165 #define INTSTS_MIII (1 << 12)
166 #define INTSTS_PHYI (1 << 11)
167 #define INTSTS_TI (1 << 10)
168 #define INTSTS_AHBE (1 << 8)
169 #define INTSTS_OTHER (1 << 4)
170 #define INTSTS_TXSQ (1 << 3)
171 #define INTSTS_RXSQ (1 << 2)
173 #define BMCTL_MT (1 << 13)
174 #define BMCTL_TT (1 << 12)
175 #define BMCTL_UNH (1 << 11)
176 #define BMCTL_TXCHR (1 << 10)
177 #define BMCTL_TXDIS (1 << 9)
178 #define BMCTL_TXEN (1 << 8)
179 #define BMCTL_EH2 (1 << 6)
180 #define BMCTL_EH1 (1 << 5)
181 #define BMCTL_EEOB (1 << 4)
182 #define BMCTL_RXCHR (1 << 2)
183 #define BMCTL_RXDIS (1 << 1)
184 #define BMCTL_RXEN (1 << 0)
186 #define BMSTS_TXACT (1 << 7)
187 #define BMSTS_TP (1 << 4)
188 #define BMSTS_RXACT (1 << 3)
189 #define BMSTS_QID_MASK 0x07
190 #define BMSTS_QID_RXDATA 0x00
191 #define BMSTS_QID_TXDATA 0x01
192 #define BMSTS_QID_RXSTS 0x02
193 #define BMSTS_QID_TXSTS 0x03
194 #define BMSTS_QID_RXDESC 0x04
195 #define BMSTS_QID_TXDESC 0x05
197 #define AFP_MASK 0x07
198 #define AFP_IAPRIMARY 0x00
199 #define AFP_IASECONDARY1 0x01
200 #define AFP_IASECONDARY2 0x02
201 #define AFP_IASECONDARY3 0x03
203 #define AFP_HASH 0x07
205 #define RXCTL_PAUSEA (1 << 20)
206 #define RXCTL_RXFCE1 (1 << 19)
207 #define RXCTL_RXFCE0 (1 << 18)
208 #define RXCTL_BCRC (1 << 17)
209 #define RXCTL_SRXON (1 << 16)
210 #define RXCTL_RCRCA (1 << 13)
211 #define RXCTL_RA (1 << 12)
212 #define RXCTL_PA (1 << 11)
213 #define RXCTL_BA (1 << 10)
214 #define RXCTL_MA (1 << 9)
215 #define RXCTL_IAHA (1 << 8)
216 #define RXCTL_IA3 (1 << 3)
217 #define RXCTL_IA2 (1 << 2)
218 #define RXCTL_IA1 (1 << 1)
219 #define RXCTL_IA0 (1 << 0)
221 #define TXCTL_DEFDIS (1 << 7)
222 #define TXCTL_MBE (1 << 6)
223 #define TXCTL_ICRC (1 << 5)
224 #define TXCTL_TPD (1 << 4)
225 #define TXCTL_OCOLL (1 << 3)
226 #define TXCTL_SP (1 << 2)
227 #define TXCTL_PB (1 << 1)
228 #define TXCTL_STXON (1 << 0)
230 #define MIICMD_REGAD_MASK (0x001F)
231 #define MIICMD_PHYAD_MASK (0x03E0)
232 #define MIICMD_OPCODE_MASK (0xC000)
233 #define MIICMD_PHYAD_8950 (0x0000)
234 #define MIICMD_OPCODE_READ (0x8000)
235 #define MIICMD_OPCODE_WRITE (0x4000)
237 #define MIISTS_BUSY (1 << 0)
240 * 0x80020000 - 0x8002FFFF: USB OHCI
242 #define USB_OFFSET 0x020000
243 #define USB_BASE (EP93XX_AHB_BASE | USB_OFFSET)
246 * 0x80030000 - 0x8003FFFF: Raster engine
248 #if (defined(CONFIG_EP9307) || defined(CONFIG_EP9312) || defined(CONFIG_EP9315))
249 #define RASTER_OFFSET 0x030000
250 #define RASTER_BASE (EP93XX_AHB_BASE | RASTER_OFFSET)
254 * 0x80040000 - 0x8004FFFF: Graphics accelerator
256 #if defined(CONFIG_EP9315)
257 #define GFX_OFFSET 0x040000
258 #define GFX_BASE (EP93XX_AHB_BASE | GFX_OFFSET)
262 * 0x80050000 - 0x8005FFFF: Reserved
266 * 0x80060000 - 0x8006FFFF: SDRAM controller
268 #define SDRAM_OFFSET 0x060000
269 #define SDRAM_BASE (EP93XX_AHB_BASE | SDRAM_OFFSET)
284 #define SDRAM_DEVCFG_EXTBUSWIDTH (1 << 2)
285 #define SDRAM_DEVCFG_BANKCOUNT (1 << 3)
286 #define SDRAM_DEVCFG_SROMLL (1 << 5)
287 #define SDRAM_DEVCFG_CASLAT_2 0x00010000
288 #define SDRAM_DEVCFG_RASTOCAS_2 0x00200000
290 #define GLCONFIG_INIT (1 << 0)
291 #define GLCONFIG_MRS (1 << 1)
292 #define GLCONFIG_SMEMBUSY (1 << 5)
293 #define GLCONFIG_LCR (1 << 6)
294 #define GLCONFIG_REARBEN (1 << 7)
295 #define GLCONFIG_CLKSHUTDOWN (1 << 30)
296 #define GLCONFIG_CKE (1 << 31)
299 * 0x80070000 - 0x8007FFFF: Reserved
303 * 0x80080000 - 0x8008FFFF: SRAM controller & PCMCIA
305 #define SMC_OFFSET 0x080000
306 #define SMC_BASE (EP93XX_AHB_BASE | SMC_OFFSET)
314 uint32_t reserved0[2];
317 #if defined(CONFIG_EP9315)
318 uint32_t pcattribute;
321 uint32_t reserved1[5];
327 #define SMC_BCR_IDCY_SHIFT 0
328 #define SMC_BCR_WST1_SHIFT 5
329 #define SMC_BCR_BLE (1 << 10)
330 #define SMC_BCR_WST2_SHIFT 11
331 #define SMC_BCR_MW_SHIFT 28
334 * 0x80090000 - 0x8009FFFF: Boot ROM
338 * 0x800A0000 - 0x800AFFFF: IDE interface
342 * 0x800B0000 - 0x800BFFFF: VIC1
346 * 0x800C0000 - 0x800CFFFF: VIC2
350 * 0x800D0000 - 0x800FFFFF: Reserved
354 * 0x80800000 - 0x8080FFFF: Reserved
358 * 0x80810000 - 0x8081FFFF: Timers
360 #define TIMER_OFFSET 0x010000
361 #define TIMER_BASE (EP93XX_APB_BASE | TIMER_OFFSET)
378 uint32_t reserved0[4];
380 uint32_t reserved1[12];
381 struct timer4 timer4;
382 uint32_t reserved2[6];
388 * 0x80820000 - 0x8082FFFF: I2S
390 #define I2S_OFFSET 0x020000
391 #define I2S_BASE (EP93XX_APB_BASE | I2S_OFFSET)
394 * 0x80830000 - 0x8083FFFF: Security
396 #define SECURITY_OFFSET 0x030000
397 #define SECURITY_BASE (EP93XX_APB_BASE | SECURITY_OFFSET)
399 #define EXTENSIONID (SECURITY_BASE + 0x2714)
402 * 0x80840000 - 0x8084FFFF: GPIO
404 #define GPIO_OFFSET 0x040000
405 #define GPIO_BASE (EP93XX_APB_BASE | GPIO_OFFSET)
429 uint32_t reserved0[2];
440 struct gpio_int pfint;
441 uint32_t reserved3[10];
442 struct gpio_int paint;
443 struct gpio_int pbint;
449 * 0x80850000 - 0x8087FFFF: Reserved
453 * 0x80880000 - 0x8088FFFF: AAC
455 #define AAC_OFFSET 0x080000
456 #define AAC_BASE (EP93XX_APB_BASE | AAC_OFFSET)
459 * 0x80890000 - 0x8089FFFF: Reserved
463 * 0x808A0000 - 0x808AFFFF: SPI
465 #define SPI_OFFSET 0x0A0000
466 #define SPI_BASE (EP93XX_APB_BASE | SPI_OFFSET)
469 * 0x808B0000 - 0x808BFFFF: IrDA
471 #define IRDA_OFFSET 0x0B0000
472 #define IRDA_BASE (EP93XX_APB_BASE | IRDA_OFFSET)
475 * 0x808C0000 - 0x808CFFFF: UART1
477 #define UART1_OFFSET 0x0C0000
478 #define UART1_BASE (EP93XX_APB_BASE | UART1_OFFSET)
481 * 0x808D0000 - 0x808DFFFF: UART2
483 #define UART2_OFFSET 0x0D0000
484 #define UART2_BASE (EP93XX_APB_BASE | UART2_OFFSET)
487 * 0x808E0000 - 0x808EFFFF: UART3
489 #define UART3_OFFSET 0x0E0000
490 #define UART3_BASE (EP93XX_APB_BASE | UART3_OFFSET)
493 * 0x808F0000 - 0x808FFFFF: Key Matrix
495 #define KEY_OFFSET 0x0F0000
496 #define KEY_BASE (EP93XX_APB_BASE | KEY_OFFSET)
499 * 0x80900000 - 0x8090FFFF: Touchscreen
501 #define TOUCH_OFFSET 0x900000
502 #define TOUCH_BASE (EP93XX_APB_BASE | TOUCH_OFFSET)
505 * 0x80910000 - 0x8091FFFF: Pulse Width Modulation
507 #define PWM_OFFSET 0x910000
508 #define PWM_BASE (EP93XX_APB_BASE | PWM_OFFSET)
511 * 0x80920000 - 0x8092FFFF: Real time clock
513 #define RTC_OFFSET 0x920000
514 #define RTC_BASE (EP93XX_APB_BASE | RTC_OFFSET)
517 * 0x80930000 - 0x8093FFFF: Syscon
519 #define SYSCON_OFFSET 0x930000
520 #define SYSCON_BASE (EP93XX_APB_BASE | SYSCON_OFFSET)
528 uint32_t reserved0[2];
533 uint32_t reserved1[6];
536 uint32_t reserved2[2];
538 uint32_t bustmstrarb;
539 uint32_t bootmodeclr;
540 uint32_t reserved3[9];
545 uint32_t keytchclkdiv;
549 uint32_t reserved5[8];
553 #define SYSCON_SCRATCH0 (SYSCON_BASE + 0x0040)
556 #define SYSCON_PWRCNT_UART_BAUD (1 << 29)
558 #define SYSCON_CLKSET_PLL_X2IPD_SHIFT 0
559 #define SYSCON_CLKSET_PLL_X2FBD2_SHIFT 5
560 #define SYSCON_CLKSET_PLL_X1FBD1_SHIFT 11
561 #define SYSCON_CLKSET_PLL_PS_SHIFT 16
562 #define SYSCON_CLKSET1_PCLK_DIV_SHIFT 18
563 #define SYSCON_CLKSET1_HCLK_DIV_SHIFT 20
564 #define SYSCON_CLKSET1_NBYP1 (1 << 23)
565 #define SYSCON_CLKSET1_FCLK_DIV_SHIFT 25
567 #define SYSCON_CLKSET2_PLL2_EN (1 << 18)
568 #define SYSCON_CLKSET2_NBYP2 (1 << 19)
569 #define SYSCON_CLKSET2_USB_DIV_SHIFT 28
571 #define SYSCON_CHIPID_REV_MASK 0xF0000000
572 #define SYSCON_DEVICECFG_SWRST (1 << 31)
575 * 0x80930000 - 0x8093FFFF: Watchdog Timer
577 #define WATCHDOG_OFFSET 0x940000
578 #define WATCHDOG_BASE (EP93XX_APB_BASE | WATCHDOG_OFFSET)
581 * 0x80950000 - 0x9000FFFF: Reserved