2 * (C) Copyright 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #define DEVICE_NOT_AVAILABLE 0
13 #define EXYNOS_CPU_NAME "Exynos"
14 #define EXYNOS4_ADDR_BASE 0x10000000
17 #define EXYNOS4_I2C_SPACING 0x10000
19 #define EXYNOS4_GPIO_PART3_BASE 0x03860000
20 #define EXYNOS4_PRO_ID 0x10000000
21 #define EXYNOS4_SYSREG_BASE 0x10010000
22 #define EXYNOS4_POWER_BASE 0x10020000
23 #define EXYNOS4_SWRESET 0x10020400
24 #define EXYNOS4_CLOCK_BASE 0x10030000
25 #define EXYNOS4_SYSTIMER_BASE 0x10050000
26 #define EXYNOS4_WATCHDOG_BASE 0x10060000
27 #define EXYNOS4_TZPC_BASE 0x10110000
28 #define EXYNOS4_MIU_BASE 0x10600000
29 #define EXYNOS4_DMC_CTRL_BASE 0x10400000
30 #define EXYNOS4_GPIO_PART2_BASE 0x11000000
31 #define EXYNOS4_GPIO_PART1_BASE 0x11400000
32 #define EXYNOS4_FIMD_BASE 0x11C00000
33 #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000
34 #define EXYNOS4_USBOTG_BASE 0x12480000
35 #define EXYNOS4_MMC_BASE 0x12510000
36 #define EXYNOS4_SROMC_BASE 0x12570000
37 #define EXYNOS4_USB_HOST_EHCI_BASE 0x12580000
38 #define EXYNOS4_USBPHY_BASE 0x125B0000
39 #define EXYNOS4_UART_BASE 0x13800000
40 #define EXYNOS4_I2C_BASE 0x13860000
41 #define EXYNOS4_ADC_BASE 0x13910000
42 #define EXYNOS4_SPI_BASE 0x13920000
43 #define EXYNOS4_PWMTIMER_BASE 0x139D0000
44 #define EXYNOS4_MODEM_BASE 0x13A00000
45 #define EXYNOS4_USBPHY_CONTROL 0x10020704
46 #define EXYNOS4_I2S_BASE 0xE2100000
48 #define EXYNOS4_GPIO_PART4_BASE DEVICE_NOT_AVAILABLE
49 #define EXYNOS4_DP_BASE DEVICE_NOT_AVAILABLE
50 #define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
51 #define EXYNOS4_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
52 #define EXYNOS4_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
53 #define EXYNOS4_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
54 #define EXYNOS4_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
55 #define EXYNOS4_USB3PHY_BASE DEVICE_NOT_AVAILABLE
58 #define EXYNOS4X12_GPIO_PART3_BASE 0x03860000
59 #define EXYNOS4X12_PRO_ID 0x10000000
60 #define EXYNOS4X12_SYSREG_BASE 0x10010000
61 #define EXYNOS4X12_POWER_BASE 0x10020000
62 #define EXYNOS4X12_SWRESET 0x10020400
63 #define EXYNOS4X12_USBPHY_CONTROL 0x10020704
64 #define EXYNOS4X12_CLOCK_BASE 0x10030000
65 #define EXYNOS4X12_SYSTIMER_BASE 0x10050000
66 #define EXYNOS4X12_WATCHDOG_BASE 0x10060000
67 #define EXYNOS4X12_TZPC_BASE 0x10110000
68 #define EXYNOS4X12_DMC_CTRL_BASE 0x10600000
69 #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000
70 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000
71 #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000
72 #define EXYNOS4X12_FIMD_BASE 0x11C00000
73 #define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000
74 #define EXYNOS4X12_USBOTG_BASE 0x12480000
75 #define EXYNOS4X12_MMC_BASE 0x12510000
76 #define EXYNOS4X12_SROMC_BASE 0x12570000
77 #define EXYNOS4X12_USB_HOST_EHCI_BASE 0x12580000
78 #define EXYNOS4X12_USBPHY_BASE 0x125B0000
79 #define EXYNOS4X12_UART_BASE 0x13800000
80 #define EXYNOS4X12_I2C_BASE 0x13860000
81 #define EXYNOS4X12_PWMTIMER_BASE 0x139D0000
83 #define EXYNOS4X12_ADC_BASE DEVICE_NOT_AVAILABLE
84 #define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
85 #define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
86 #define EXYNOS4X12_I2S_BASE DEVICE_NOT_AVAILABLE
87 #define EXYNOS4X12_SPI_BASE DEVICE_NOT_AVAILABLE
88 #define EXYNOS4X12_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
89 #define EXYNOS4X12_ACE_SFR_BASE DEVICE_NOT_AVAILABLE
90 #define EXYNOS4X12_DMC_PHY_BASE DEVICE_NOT_AVAILABLE
91 #define EXYNOS4X12_AUDIOSS_BASE DEVICE_NOT_AVAILABLE
92 #define EXYNOS4X12_USB_HOST_XHCI_BASE DEVICE_NOT_AVAILABLE
93 #define EXYNOS4X12_USB3PHY_BASE DEVICE_NOT_AVAILABLE
96 #define EXYNOS5_I2C_SPACING 0x10000
98 #define EXYNOS5_AUDIOSS_BASE 0x03810000
99 #define EXYNOS5_GPIO_PART4_BASE 0x03860000
100 #define EXYNOS5_PRO_ID 0x10000000
101 #define EXYNOS5_CLOCK_BASE 0x10010000
102 #define EXYNOS5_POWER_BASE 0x10040000
103 #define EXYNOS5_SWRESET 0x10040400
104 #define EXYNOS5_SYSREG_BASE 0x10050000
105 #define EXYNOS5_TZPC_BASE 0x10100000
106 #define EXYNOS5_WATCHDOG_BASE 0x101D0000
107 #define EXYNOS5_ACE_SFR_BASE 0x10830000
108 #define EXYNOS5_DMC_PHY_BASE 0x10C00000
109 #define EXYNOS5_GPIO_PART3_BASE 0x10D10000
110 #define EXYNOS5_DMC_CTRL_BASE 0x10DD0000
111 #define EXYNOS5_GPIO_PART1_BASE 0x11400000
112 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000
113 #define EXYNOS5_USB_HOST_XHCI_BASE 0x12000000
114 #define EXYNOS5_USB3PHY_BASE 0x12100000
115 #define EXYNOS5_USB_HOST_EHCI_BASE 0x12110000
116 #define EXYNOS5_USBPHY_BASE 0x12130000
117 #define EXYNOS5_USBOTG_BASE 0x12140000
118 #define EXYNOS5_MMC_BASE 0x12200000
119 #define EXYNOS5_SROMC_BASE 0x12250000
120 #define EXYNOS5_UART_BASE 0x12C00000
121 #define EXYNOS5_I2C_BASE 0x12C60000
122 #define EXYNOS5_SPI_BASE 0x12D20000
123 #define EXYNOS5_I2S_BASE 0x12D60000
124 #define EXYNOS5_PWMTIMER_BASE 0x12DD0000
125 #define EXYNOS5_SPI_ISP_BASE 0x131A0000
126 #define EXYNOS5_GPIO_PART2_BASE 0x13400000
127 #define EXYNOS5_FIMD_BASE 0x14400000
128 #define EXYNOS5_DP_BASE 0x145B0000
130 #define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
131 #define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
135 /* CPU detection macros */
136 extern unsigned int s5p_cpu_id;
137 extern unsigned int s5p_cpu_rev;
139 static inline int s5p_get_cpu_rev(void)
144 static inline void s5p_set_cpu_id(void)
146 unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
150 /* Exynos4210 EVT0 */
155 /* Exynos4210 EVT1 */
169 static inline char *s5p_get_cpu_name(void)
171 return EXYNOS_CPU_NAME;
174 #define IS_SAMSUNG_TYPE(type, id) \
175 static inline int __attribute__((no_instrument_function)) cpu_is_##type(void) \
177 return (s5p_cpu_id >> 12) == id; \
180 IS_SAMSUNG_TYPE(exynos4, 0x4)
181 IS_SAMSUNG_TYPE(exynos5, 0x5)
183 #define IS_EXYNOS_TYPE(type, id) \
184 static inline int __attribute__((no_instrument_function)) \
185 proid_is_##type(void) \
187 return s5p_cpu_id == id; \
190 IS_EXYNOS_TYPE(exynos4210, 0x4210)
191 IS_EXYNOS_TYPE(exynos4412, 0x4412)
192 IS_EXYNOS_TYPE(exynos5250, 0x5250)
194 #define SAMSUNG_BASE(device, base) \
195 static inline unsigned int __attribute__((no_instrument_function)) \
196 samsung_get_base_##device(void) \
198 if (cpu_is_exynos4()) { \
199 if (proid_is_exynos4412()) \
200 return EXYNOS4X12_##base; \
201 return EXYNOS4_##base; \
202 } else if (cpu_is_exynos5()) { \
203 return EXYNOS5_##base; \
208 SAMSUNG_BASE(adc, ADC_BASE)
209 SAMSUNG_BASE(clock, CLOCK_BASE)
210 SAMSUNG_BASE(ace_sfr, ACE_SFR_BASE)
211 SAMSUNG_BASE(dp, DP_BASE)
212 SAMSUNG_BASE(sysreg, SYSREG_BASE)
213 SAMSUNG_BASE(fimd, FIMD_BASE)
214 SAMSUNG_BASE(i2c, I2C_BASE)
215 SAMSUNG_BASE(i2s, I2S_BASE)
216 SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
217 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
218 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
219 SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
220 SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
221 SAMSUNG_BASE(pro_id, PRO_ID)
222 SAMSUNG_BASE(mmc, MMC_BASE)
223 SAMSUNG_BASE(modem, MODEM_BASE)
224 SAMSUNG_BASE(sromc, SROMC_BASE)
225 SAMSUNG_BASE(swreset, SWRESET)
226 SAMSUNG_BASE(timer, PWMTIMER_BASE)
227 SAMSUNG_BASE(uart, UART_BASE)
228 SAMSUNG_BASE(usb_phy, USBPHY_BASE)
229 SAMSUNG_BASE(usb3_phy, USB3PHY_BASE)
230 SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
231 SAMSUNG_BASE(usb_xhci, USB_HOST_XHCI_BASE)
232 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
233 SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
234 SAMSUNG_BASE(power, POWER_BASE)
235 SAMSUNG_BASE(spi, SPI_BASE)
236 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
237 SAMSUNG_BASE(tzpc, TZPC_BASE)
238 SAMSUNG_BASE(dmc_ctrl, DMC_CTRL_BASE)
239 SAMSUNG_BASE(dmc_phy, DMC_PHY_BASE)
240 SAMSUNG_BASE(audio_ass, AUDIOSS_BASE)
243 #endif /* _EXYNOS4_CPU_H */