git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-exynos/cpu.h

   1 /*
   2  * (C) Copyright 2010 Samsung Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  *
  20  */
  21
  22 #ifndef _EXYNOS4_CPU_H
  23 #define _EXYNOS4_CPU_H
  24
  25 #define DEVICE_NOT_AVAILABLE            0
  26
  27 #define EXYNOS_CPU_NAME                 "Exynos"
  28 #define EXYNOS4_ADDR_BASE               0x10000000
  29
  30 /* EXYNOS4 Common*/
  31 #define EXYNOS4_I2C_SPACING             0x10000
  32
  33 #define EXYNOS4_GPIO_PART3_BASE         0x03860000
  34 #define EXYNOS4_PRO_ID                  0x10000000
  35 #define EXYNOS4_SYSREG_BASE             0x10010000
  36 #define EXYNOS4_POWER_BASE              0x10020000
  37 #define EXYNOS4_SWRESET                 0x10020400
  38 #define EXYNOS4_CLOCK_BASE              0x10030000
  39 #define EXYNOS4_SYSTIMER_BASE           0x10050000
  40 #define EXYNOS4_WATCHDOG_BASE           0x10060000
  41 #define EXYNOS4_MIU_BASE                0x10600000
  42 #define EXYNOS4_DMC0_BASE               0x10400000
  43 #define EXYNOS4_DMC1_BASE               0x10410000
  44 #define EXYNOS4_GPIO_PART2_BASE         0x11000000
  45 #define EXYNOS4_GPIO_PART1_BASE         0x11400000
  46 #define EXYNOS4_FIMD_BASE               0x11C00000
  47 #define EXYNOS4_MIPI_DSIM_BASE          0x11C80000
  48 #define EXYNOS4_USBOTG_BASE             0x12480000
  49 #define EXYNOS4_MMC_BASE                0x12510000
  50 #define EXYNOS4_SROMC_BASE              0x12570000
  51 #define EXYNOS4_USB_HOST_EHCI_BASE      0x12580000
  52 #define EXYNOS4_USBPHY_BASE             0x125B0000
  53 #define EXYNOS4_UART_BASE               0x13800000
  54 #define EXYNOS4_I2C_BASE                0x13860000
  55 #define EXYNOS4_ADC_BASE                0x13910000
  56 #define EXYNOS4_SPI_BASE                0x13920000
  57 #define EXYNOS4_PWMTIMER_BASE           0x139D0000
  58 #define EXYNOS4_MODEM_BASE              0x13A00000
  59 #define EXYNOS4_USBPHY_CONTROL          0x10020704
  60 #define EXYNOS4_I2S_BASE                0xE2100000
  61
  62 #define EXYNOS4_GPIO_PART4_BASE         DEVICE_NOT_AVAILABLE
  63 #define EXYNOS4_DP_BASE                 DEVICE_NOT_AVAILABLE
  64 #define EXYNOS4_SPI_ISP_BASE            DEVICE_NOT_AVAILABLE
  65
  66 /* EXYNOS4X12 */
  67 #define EXYNOS4X12_GPIO_PART3_BASE      0x03860000
  68 #define EXYNOS4X12_PRO_ID               0x10000000
  69 #define EXYNOS4X12_SYSREG_BASE          0x10010000
  70 #define EXYNOS4X12_POWER_BASE           0x10020000
  71 #define EXYNOS4X12_SWRESET              0x10020400
  72 #define EXYNOS4X12_USBPHY_CONTROL       0x10020704
  73 #define EXYNOS4X12_CLOCK_BASE           0x10030000
  74 #define EXYNOS4X12_SYSTIMER_BASE        0x10050000
  75 #define EXYNOS4X12_WATCHDOG_BASE        0x10060000
  76 #define EXYNOS4X12_DMC0_BASE            0x10600000
  77 #define EXYNOS4X12_DMC1_BASE            0x10610000
  78 #define EXYNOS4X12_GPIO_PART4_BASE      0x106E0000
  79 #define EXYNOS4X12_GPIO_PART2_BASE      0x11000000
  80 #define EXYNOS4X12_GPIO_PART1_BASE      0x11400000
  81 #define EXYNOS4X12_FIMD_BASE            0x11C00000
  82 #define EXYNOS4X12_MIPI_DSIM_BASE       0x11C80000
  83 #define EXYNOS4X12_USBOTG_BASE          0x12480000
  84 #define EXYNOS4X12_MMC_BASE             0x12510000
  85 #define EXYNOS4X12_SROMC_BASE           0x12570000
  86 #define EXYNOS4X12_USB_HOST_EHCI_BASE   0x12580000
  87 #define EXYNOS4X12_USBPHY_BASE          0x125B0000
  88 #define EXYNOS4X12_UART_BASE            0x13800000
  89 #define EXYNOS4X12_I2C_BASE             0x13860000
  90 #define EXYNOS4X12_PWMTIMER_BASE        0x139D0000
  91
  92 #define EXYNOS4X12_ADC_BASE             DEVICE_NOT_AVAILABLE
  93 #define EXYNOS4X12_DP_BASE              DEVICE_NOT_AVAILABLE
  94 #define EXYNOS4X12_MODEM_BASE           DEVICE_NOT_AVAILABLE
  95 #define EXYNOS4X12_I2S_BASE            DEVICE_NOT_AVAILABLE
  96 #define EXYNOS4X12_SPI_BASE            DEVICE_NOT_AVAILABLE
  97 #define EXYNOS4X12_SPI_ISP_BASE                DEVICE_NOT_AVAILABLE
  98
  99 /* EXYNOS5 Common*/
 100 #define EXYNOS5_I2C_SPACING             0x10000
 101
 102 #define EXYNOS5_GPIO_PART4_BASE         0x03860000
 103 #define EXYNOS5_PRO_ID                  0x10000000
 104 #define EXYNOS5_CLOCK_BASE              0x10010000
 105 #define EXYNOS5_POWER_BASE              0x10040000
 106 #define EXYNOS5_SWRESET                 0x10040400
 107 #define EXYNOS5_SYSREG_BASE             0x10050000
 108 #define EXYNOS5_WATCHDOG_BASE           0x101D0000
 109 #define EXYNOS5_DMC_PHY0_BASE           0x10C00000
 110 #define EXYNOS5_DMC_PHY1_BASE           0x10C10000
 111 #define EXYNOS5_GPIO_PART3_BASE         0x10D10000
 112 #define EXYNOS5_DMC_CTRL_BASE           0x10DD0000
 113 #define EXYNOS5_GPIO_PART1_BASE         0x11400000
 114 #define EXYNOS5_MIPI_DSIM_BASE          0x11D00000
 115 #define EXYNOS5_USB_HOST_EHCI_BASE      0x12110000
 116 #define EXYNOS5_USBPHY_BASE             0x12130000
 117 #define EXYNOS5_USBOTG_BASE             0x12140000
 118 #define EXYNOS5_MMC_BASE                0x12200000
 119 #define EXYNOS5_SROMC_BASE              0x12250000
 120 #define EXYNOS5_UART_BASE               0x12C00000
 121 #define EXYNOS5_I2C_BASE                0x12C60000
 122 #define EXYNOS5_SPI_BASE                0x12D20000
 123 #define EXYNOS5_I2S_BASE                0x12D60000
 124 #define EXYNOS5_PWMTIMER_BASE           0x12DD0000
 125 #define EXYNOS5_SPI_ISP_BASE            0x131A0000
 126 #define EXYNOS5_GPIO_PART2_BASE         0x13400000
 127 #define EXYNOS5_FIMD_BASE               0x14400000
 128 #define EXYNOS5_DP_BASE                 0x145B0000
 129
 130 #define EXYNOS5_ADC_BASE                DEVICE_NOT_AVAILABLE
 131 #define EXYNOS5_MODEM_BASE              DEVICE_NOT_AVAILABLE
 132
 133 #ifndef __ASSEMBLY__
 134 #include <asm/io.h>
 135 /* CPU detection macros */
 136 extern unsigned int s5p_cpu_id;
 137 extern unsigned int s5p_cpu_rev;
 138
 139 static inline int s5p_get_cpu_rev(void)
 140 {
 141         return s5p_cpu_rev;
 142 }
 143
 144 static inline void s5p_set_cpu_id(void)
 145 {
 146         unsigned int pro_id = (readl(EXYNOS4_PRO_ID) & 0x00FFF000) >> 12;
 147
 148         switch (pro_id) {
 149         case 0x200:
 150                 /* Exynos4210 EVT0 */
 151                 s5p_cpu_id = 0x4210;
 152                 s5p_cpu_rev = 0;
 153                 break;
 154         case 0x210:
 155                 /* Exynos4210 EVT1 */
 156                 s5p_cpu_id = 0x4210;
 157                 break;
 158         case 0x412:
 159                 /* Exynos4412 */
 160                 s5p_cpu_id = 0x4412;
 161                 break;
 162         case 0x520:
 163                 /* Exynos5250 */
 164                 s5p_cpu_id = 0x5250;
 165                 break;
 166         }
 167 }
 168
 169 static inline char *s5p_get_cpu_name(void)
 170 {
 171         return EXYNOS_CPU_NAME;
 172 }
 173
 174 #define IS_SAMSUNG_TYPE(type, id)                       \
 175 static inline int cpu_is_##type(void)                   \
 176 {                                                       \
 177         return (s5p_cpu_id >> 12) == id;                \
 178 }
 179
 180 IS_SAMSUNG_TYPE(exynos4, 0x4)
 181 IS_SAMSUNG_TYPE(exynos5, 0x5)
 182
 183 #define IS_EXYNOS_TYPE(type, id)                        \
 184 static inline int proid_is_##type(void)                 \
 185 {                                                       \
 186         return s5p_cpu_id == id;                        \
 187 }
 188
 189 IS_EXYNOS_TYPE(exynos4210, 0x4210)
 190 IS_EXYNOS_TYPE(exynos4412, 0x4412)
 191 IS_EXYNOS_TYPE(exynos5250, 0x5250)
 192
 193 #define SAMSUNG_BASE(device, base)                              \
 194 static inline unsigned int samsung_get_base_##device(void)      \
 195 {                                                               \
 196         if (cpu_is_exynos4()) {                                 \
 197                 if (proid_is_exynos4412())                      \
 198                         return EXYNOS4X12_##base;               \
 199                 return EXYNOS4_##base;                          \
 200         } else if (cpu_is_exynos5()) {                          \
 201                 return EXYNOS5_##base;                          \
 202         }                                                       \
 203         return 0;                                               \
 204 }
 205
 206 SAMSUNG_BASE(adc, ADC_BASE)
 207 SAMSUNG_BASE(clock, CLOCK_BASE)
 208 SAMSUNG_BASE(dp, DP_BASE)
 209 SAMSUNG_BASE(sysreg, SYSREG_BASE)
 210 SAMSUNG_BASE(fimd, FIMD_BASE)
 211 SAMSUNG_BASE(i2c, I2C_BASE)
 212 SAMSUNG_BASE(i2s, I2S_BASE)
 213 SAMSUNG_BASE(mipi_dsim, MIPI_DSIM_BASE)
 214 SAMSUNG_BASE(gpio_part1, GPIO_PART1_BASE)
 215 SAMSUNG_BASE(gpio_part2, GPIO_PART2_BASE)
 216 SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE)
 217 SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE)
 218 SAMSUNG_BASE(pro_id, PRO_ID)
 219 SAMSUNG_BASE(mmc, MMC_BASE)
 220 SAMSUNG_BASE(modem, MODEM_BASE)
 221 SAMSUNG_BASE(sromc, SROMC_BASE)
 222 SAMSUNG_BASE(swreset, SWRESET)
 223 SAMSUNG_BASE(timer, PWMTIMER_BASE)
 224 SAMSUNG_BASE(uart, UART_BASE)
 225 SAMSUNG_BASE(usb_phy, USBPHY_BASE)
 226 SAMSUNG_BASE(usb_ehci, USB_HOST_EHCI_BASE)
 227 SAMSUNG_BASE(usb_otg, USBOTG_BASE)
 228 SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 229 SAMSUNG_BASE(power, POWER_BASE)
 230 SAMSUNG_BASE(spi, SPI_BASE)
 231 SAMSUNG_BASE(spi_isp, SPI_ISP_BASE)
 232 #endif
 233
 234 #endif  /* _EXYNOS4_CPU_H */