2 * (C) Copyright 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef __ASM_ARCH_GPIO_H
22 #define __ASM_ARCH_GPIO_H
25 struct s5p_gpio_bank {
31 unsigned int pdn_pull;
32 unsigned char res1[8];
35 struct exynos4_gpio_part1 {
36 struct s5p_gpio_bank a0;
37 struct s5p_gpio_bank a1;
38 struct s5p_gpio_bank b;
39 struct s5p_gpio_bank c0;
40 struct s5p_gpio_bank c1;
41 struct s5p_gpio_bank d0;
42 struct s5p_gpio_bank d1;
43 struct s5p_gpio_bank e0;
44 struct s5p_gpio_bank e1;
45 struct s5p_gpio_bank e2;
46 struct s5p_gpio_bank e3;
47 struct s5p_gpio_bank e4;
48 struct s5p_gpio_bank f0;
49 struct s5p_gpio_bank f1;
50 struct s5p_gpio_bank f2;
51 struct s5p_gpio_bank f3;
54 struct exynos4_gpio_part2 {
55 struct s5p_gpio_bank j0;
56 struct s5p_gpio_bank j1;
57 struct s5p_gpio_bank k0;
58 struct s5p_gpio_bank k1;
59 struct s5p_gpio_bank k2;
60 struct s5p_gpio_bank k3;
61 struct s5p_gpio_bank l0;
62 struct s5p_gpio_bank l1;
63 struct s5p_gpio_bank l2;
64 struct s5p_gpio_bank y0;
65 struct s5p_gpio_bank y1;
66 struct s5p_gpio_bank y2;
67 struct s5p_gpio_bank y3;
68 struct s5p_gpio_bank y4;
69 struct s5p_gpio_bank y5;
70 struct s5p_gpio_bank y6;
71 struct s5p_gpio_bank res1[80];
72 struct s5p_gpio_bank x0;
73 struct s5p_gpio_bank x1;
74 struct s5p_gpio_bank x2;
75 struct s5p_gpio_bank x3;
78 struct exynos4_gpio_part3 {
79 struct s5p_gpio_bank z;
82 struct exynos4x12_gpio_part1 {
83 struct s5p_gpio_bank a0;
84 struct s5p_gpio_bank a1;
85 struct s5p_gpio_bank b;
86 struct s5p_gpio_bank c0;
87 struct s5p_gpio_bank c1;
88 struct s5p_gpio_bank d0;
89 struct s5p_gpio_bank d1;
90 struct s5p_gpio_bank res1[0x5];
91 struct s5p_gpio_bank f0;
92 struct s5p_gpio_bank f1;
93 struct s5p_gpio_bank f2;
94 struct s5p_gpio_bank f3;
95 struct s5p_gpio_bank res2[0x2];
96 struct s5p_gpio_bank j0;
97 struct s5p_gpio_bank j1;
100 struct exynos4x12_gpio_part2 {
101 struct s5p_gpio_bank res1[0x2];
102 struct s5p_gpio_bank k0;
103 struct s5p_gpio_bank k1;
104 struct s5p_gpio_bank k2;
105 struct s5p_gpio_bank k3;
106 struct s5p_gpio_bank l0;
107 struct s5p_gpio_bank l1;
108 struct s5p_gpio_bank l2;
109 struct s5p_gpio_bank y0;
110 struct s5p_gpio_bank y1;
111 struct s5p_gpio_bank y2;
112 struct s5p_gpio_bank y3;
113 struct s5p_gpio_bank y4;
114 struct s5p_gpio_bank y5;
115 struct s5p_gpio_bank y6;
116 struct s5p_gpio_bank res2[0x3];
117 struct s5p_gpio_bank m0;
118 struct s5p_gpio_bank m1;
119 struct s5p_gpio_bank m2;
120 struct s5p_gpio_bank m3;
121 struct s5p_gpio_bank m4;
122 struct s5p_gpio_bank res3[0x48];
123 struct s5p_gpio_bank x0;
124 struct s5p_gpio_bank x1;
125 struct s5p_gpio_bank x2;
126 struct s5p_gpio_bank x3;
129 struct exynos4x12_gpio_part3 {
130 struct s5p_gpio_bank z;
133 struct exynos4x12_gpio_part4 {
134 struct s5p_gpio_bank v0;
135 struct s5p_gpio_bank v1;
136 struct s5p_gpio_bank res1[0x1];
137 struct s5p_gpio_bank v2;
138 struct s5p_gpio_bank v3;
139 struct s5p_gpio_bank res2[0x1];
140 struct s5p_gpio_bank v4;
143 struct exynos5_gpio_part1 {
144 struct s5p_gpio_bank a0;
145 struct s5p_gpio_bank a1;
146 struct s5p_gpio_bank a2;
147 struct s5p_gpio_bank b0;
148 struct s5p_gpio_bank b1;
149 struct s5p_gpio_bank b2;
150 struct s5p_gpio_bank b3;
151 struct s5p_gpio_bank c0;
152 struct s5p_gpio_bank c1;
153 struct s5p_gpio_bank c2;
154 struct s5p_gpio_bank c3;
155 struct s5p_gpio_bank d0;
156 struct s5p_gpio_bank d1;
157 struct s5p_gpio_bank y0;
158 struct s5p_gpio_bank y1;
159 struct s5p_gpio_bank y2;
160 struct s5p_gpio_bank y3;
161 struct s5p_gpio_bank y4;
162 struct s5p_gpio_bank y5;
163 struct s5p_gpio_bank y6;
164 struct s5p_gpio_bank res1[0x3];
165 struct s5p_gpio_bank c4;
166 struct s5p_gpio_bank res2[0x48];
167 struct s5p_gpio_bank x0;
168 struct s5p_gpio_bank x1;
169 struct s5p_gpio_bank x2;
170 struct s5p_gpio_bank x3;
173 struct exynos5_gpio_part2 {
174 struct s5p_gpio_bank e0;
175 struct s5p_gpio_bank e1;
176 struct s5p_gpio_bank f0;
177 struct s5p_gpio_bank f1;
178 struct s5p_gpio_bank g0;
179 struct s5p_gpio_bank g1;
180 struct s5p_gpio_bank g2;
181 struct s5p_gpio_bank h0;
182 struct s5p_gpio_bank h1;
185 struct exynos5_gpio_part3 {
186 struct s5p_gpio_bank v0;
187 struct s5p_gpio_bank v1;
188 struct s5p_gpio_bank res1[0x1];
189 struct s5p_gpio_bank v2;
190 struct s5p_gpio_bank v3;
191 struct s5p_gpio_bank res2[0x1];
192 struct s5p_gpio_bank v4;
195 struct exynos5_gpio_part4 {
196 struct s5p_gpio_bank z;
200 void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
201 void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
202 void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
203 void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
204 unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
205 void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
206 void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
207 void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
209 /* GPIO pins per bank */
210 #define GPIO_PER_BANK 8
212 #define exynos4_gpio_part1_get_nr(bank, pin) \
213 ((((((unsigned int) &(((struct exynos4_gpio_part1 *) \
214 EXYNOS4_GPIO_PART1_BASE)->bank)) \
215 - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
216 * GPIO_PER_BANK) + pin)
218 #define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
219 / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
221 #define exynos4_gpio_part2_get_nr(bank, pin) \
222 (((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
223 EXYNOS4_GPIO_PART2_BASE)->bank)) \
224 - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
225 * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
227 #define exynos4x12_gpio_part1_get_nr(bank, pin) \
228 ((((((unsigned int) &(((struct exynos4x12_gpio_part1 *) \
229 EXYNOS4X12_GPIO_PART1_BASE)->bank)) \
230 - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
231 * GPIO_PER_BANK) + pin)
233 #define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \
234 / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
236 #define exynos4x12_gpio_part2_get_nr(bank, pin) \
237 (((((((unsigned int) &(((struct exynos4x12_gpio_part2 *) \
238 EXYNOS4X12_GPIO_PART2_BASE)->bank)) \
239 - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
240 * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX)
242 #define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \
243 / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
245 #define exynos4x12_gpio_part3_get_nr(bank, pin) \
246 (((((((unsigned int) &(((struct exynos4x12_gpio_part3 *) \
247 EXYNOS4X12_GPIO_PART3_BASE)->bank)) \
248 - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
249 * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX)
251 #define exynos5_gpio_part1_get_nr(bank, pin) \
252 ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
253 EXYNOS5_GPIO_PART1_BASE)->bank)) \
254 - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
255 * GPIO_PER_BANK) + pin)
257 #define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \
258 / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
260 #define exynos5_gpio_part2_get_nr(bank, pin) \
261 (((((((unsigned int) &(((struct exynos5_gpio_part2 *) \
262 EXYNOS5_GPIO_PART2_BASE)->bank)) \
263 - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
264 * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX)
266 #define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \
267 / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
269 #define exynos5_gpio_part3_get_nr(bank, pin) \
270 (((((((unsigned int) &(((struct exynos5_gpio_part3 *) \
271 EXYNOS5_GPIO_PART3_BASE)->bank)) \
272 - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
273 * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
275 static inline unsigned int s5p_gpio_base(int nr)
277 if (cpu_is_exynos5()) {
278 if (nr < EXYNOS5_GPIO_PART1_MAX)
279 return EXYNOS5_GPIO_PART1_BASE;
280 else if (nr < EXYNOS5_GPIO_PART2_MAX)
281 return EXYNOS5_GPIO_PART2_BASE;
283 return EXYNOS5_GPIO_PART3_BASE;
285 } else if (cpu_is_exynos4()) {
286 if (nr < EXYNOS4_GPIO_PART1_MAX)
287 return EXYNOS4_GPIO_PART1_BASE;
289 return EXYNOS4_GPIO_PART2_BASE;
295 static inline unsigned int s5p_gpio_part_max(int nr)
297 if (cpu_is_exynos5()) {
298 if (nr < EXYNOS5_GPIO_PART1_MAX)
300 else if (nr < EXYNOS5_GPIO_PART2_MAX)
301 return EXYNOS5_GPIO_PART1_MAX;
303 return EXYNOS5_GPIO_PART2_MAX;
305 } else if (cpu_is_exynos4()) {
306 if (nr < EXYNOS4_GPIO_PART1_MAX)
309 return EXYNOS4_GPIO_PART1_MAX;
316 /* Pin configurations */
317 #define GPIO_INPUT 0x0
318 #define GPIO_OUTPUT 0x1
320 #define GPIO_FUNC(x) (x)
323 #define GPIO_PULL_NONE 0x0
324 #define GPIO_PULL_DOWN 0x1
325 #define GPIO_PULL_UP 0x3
327 /* Drive Strength level */
328 #define GPIO_DRV_1X 0x0
329 #define GPIO_DRV_3X 0x1
330 #define GPIO_DRV_2X 0x2
331 #define GPIO_DRV_4X 0x3
332 #define GPIO_DRV_FAST 0x0
333 #define GPIO_DRV_SLOW 0x1