2 * (C) Copyright 2010 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 #ifndef __ASM_ARCH_GPIO_H
22 #define __ASM_ARCH_GPIO_H
25 struct s5p_gpio_bank {
31 unsigned int pdn_pull;
32 unsigned char res1[8];
35 struct exynos4_gpio_part1 {
36 struct s5p_gpio_bank a0;
37 struct s5p_gpio_bank a1;
38 struct s5p_gpio_bank b;
39 struct s5p_gpio_bank c0;
40 struct s5p_gpio_bank c1;
41 struct s5p_gpio_bank d0;
42 struct s5p_gpio_bank d1;
43 struct s5p_gpio_bank e0;
44 struct s5p_gpio_bank e1;
45 struct s5p_gpio_bank e2;
46 struct s5p_gpio_bank e3;
47 struct s5p_gpio_bank e4;
48 struct s5p_gpio_bank f0;
49 struct s5p_gpio_bank f1;
50 struct s5p_gpio_bank f2;
51 struct s5p_gpio_bank f3;
54 struct exynos4_gpio_part2 {
55 struct s5p_gpio_bank j0;
56 struct s5p_gpio_bank j1;
57 struct s5p_gpio_bank k0;
58 struct s5p_gpio_bank k1;
59 struct s5p_gpio_bank k2;
60 struct s5p_gpio_bank k3;
61 struct s5p_gpio_bank l0;
62 struct s5p_gpio_bank l1;
63 struct s5p_gpio_bank l2;
64 struct s5p_gpio_bank y0;
65 struct s5p_gpio_bank y1;
66 struct s5p_gpio_bank y2;
67 struct s5p_gpio_bank y3;
68 struct s5p_gpio_bank y4;
69 struct s5p_gpio_bank y5;
70 struct s5p_gpio_bank y6;
71 struct s5p_gpio_bank res1[80];
72 struct s5p_gpio_bank x0;
73 struct s5p_gpio_bank x1;
74 struct s5p_gpio_bank x2;
75 struct s5p_gpio_bank x3;
78 struct exynos4_gpio_part3 {
79 struct s5p_gpio_bank z;
82 struct exynos5_gpio_part1 {
83 struct s5p_gpio_bank a0;
84 struct s5p_gpio_bank a1;
85 struct s5p_gpio_bank a2;
86 struct s5p_gpio_bank b0;
87 struct s5p_gpio_bank b1;
88 struct s5p_gpio_bank b2;
89 struct s5p_gpio_bank b3;
90 struct s5p_gpio_bank c0;
91 struct s5p_gpio_bank c1;
92 struct s5p_gpio_bank c2;
93 struct s5p_gpio_bank c3;
94 struct s5p_gpio_bank d0;
95 struct s5p_gpio_bank d1;
96 struct s5p_gpio_bank y0;
97 struct s5p_gpio_bank y1;
98 struct s5p_gpio_bank y2;
99 struct s5p_gpio_bank y3;
100 struct s5p_gpio_bank y4;
101 struct s5p_gpio_bank y5;
102 struct s5p_gpio_bank y6;
103 struct s5p_gpio_bank res1[0x3];
104 struct s5p_gpio_bank c4;
105 struct s5p_gpio_bank res2[0x48];
106 struct s5p_gpio_bank x0;
107 struct s5p_gpio_bank x1;
108 struct s5p_gpio_bank x2;
109 struct s5p_gpio_bank x3;
112 struct exynos5_gpio_part2 {
113 struct s5p_gpio_bank e0;
114 struct s5p_gpio_bank e1;
115 struct s5p_gpio_bank f0;
116 struct s5p_gpio_bank f1;
117 struct s5p_gpio_bank g0;
118 struct s5p_gpio_bank g1;
119 struct s5p_gpio_bank g2;
120 struct s5p_gpio_bank h0;
121 struct s5p_gpio_bank h1;
124 struct exynos5_gpio_part3 {
125 struct s5p_gpio_bank v0;
126 struct s5p_gpio_bank v1;
127 struct s5p_gpio_bank res1[0x1];
128 struct s5p_gpio_bank v2;
129 struct s5p_gpio_bank v3;
130 struct s5p_gpio_bank res2[0x1];
131 struct s5p_gpio_bank v4;
134 struct exynos5_gpio_part4 {
135 struct s5p_gpio_bank z;
139 void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
140 void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
141 void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
142 void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
143 unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
144 void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
145 void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
146 void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
148 /* GPIO pins per bank */
149 #define GPIO_PER_BANK 8
151 #define exynos4_gpio_part1_get_nr(bank, pin) \
152 ((((((unsigned int) &(((struct exynos4_gpio_part1 *) \
153 EXYNOS4_GPIO_PART1_BASE)->bank)) \
154 - EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
155 * GPIO_PER_BANK) + pin)
157 #define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
158 / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
160 #define exynos4_gpio_part2_get_nr(bank, pin) \
161 (((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
162 EXYNOS4_GPIO_PART2_BASE)->bank)) \
163 - EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
164 * GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
166 #define exynos5_gpio_part1_get_nr(bank, pin) \
167 ((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
168 EXYNOS5_GPIO_PART1_BASE)->bank)) \
169 - EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
170 * GPIO_PER_BANK) + pin)
172 #define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \
173 / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
175 #define exynos5_gpio_part2_get_nr(bank, pin) \
176 (((((((unsigned int) &(((struct exynos5_gpio_part2 *) \
177 EXYNOS5_GPIO_PART2_BASE)->bank)) \
178 - EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
179 * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX)
181 #define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \
182 / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
184 #define exynos5_gpio_part3_get_nr(bank, pin) \
185 (((((((unsigned int) &(((struct exynos5_gpio_part3 *) \
186 EXYNOS5_GPIO_PART3_BASE)->bank)) \
187 - EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
188 * GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
190 static inline unsigned int s5p_gpio_base(int nr)
192 if (cpu_is_exynos5()) {
193 if (nr < EXYNOS5_GPIO_PART1_MAX)
194 return EXYNOS5_GPIO_PART1_BASE;
195 else if (nr < EXYNOS5_GPIO_PART2_MAX)
196 return EXYNOS5_GPIO_PART2_BASE;
198 return EXYNOS5_GPIO_PART3_BASE;
200 } else if (cpu_is_exynos4()) {
201 if (nr < EXYNOS4_GPIO_PART1_MAX)
202 return EXYNOS4_GPIO_PART1_BASE;
204 return EXYNOS4_GPIO_PART2_BASE;
212 /* Pin configurations */
213 #define GPIO_INPUT 0x0
214 #define GPIO_OUTPUT 0x1
216 #define GPIO_FUNC(x) (x)
219 #define GPIO_PULL_NONE 0x0
220 #define GPIO_PULL_DOWN 0x1
221 #define GPIO_PULL_UP 0x3
223 /* Drive Strength level */
224 #define GPIO_DRV_1X 0x0
225 #define GPIO_DRV_3X 0x1
226 #define GPIO_DRV_2X 0x2
227 #define GPIO_DRV_4X 0x3
228 #define GPIO_DRV_FAST 0x0
229 #define GPIO_DRV_SLOW 0x1