2 * Copyright 2014-2015, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _FSL_LAYERSCAPE_CPU_H
8 #define _FSL_LAYERSCAPE_CPU_H
10 static struct cpu_type cpu_type_list[] = {
11 CPU_TYPE_ENTRY(LS2085, LS2085, 8),
12 CPU_TYPE_ENTRY(LS2080, LS2080, 8),
13 CPU_TYPE_ENTRY(LS2045, LS2045, 4),
16 #ifndef CONFIG_SYS_DCACHE_OFF
18 #define SECTION_SHIFT_L0 39UL
19 #define SECTION_SHIFT_L1 30UL
20 #define SECTION_SHIFT_L2 21UL
21 #define BLOCK_SIZE_L0 0x8000000000
22 #define BLOCK_SIZE_L1 0x40000000
23 #define BLOCK_SIZE_L2 0x200000
24 #define NUM_OF_ENTRY 512
25 #define TCR_EL2_PS_40BIT (2 << 16)
27 #define LAYERSCAPE_VA_BITS (40)
28 #define LAYERSCAPE_TCR (TCR_TG0_4K | \
33 TCR_T0SZ(LAYERSCAPE_VA_BITS))
34 #define LAYERSCAPE_TCR_FINAL (TCR_TG0_4K | \
39 TCR_T0SZ(LAYERSCAPE_VA_BITS))
41 #ifdef CONFIG_FSL_LSCH3
42 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
43 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
44 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
45 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
46 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
47 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
48 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
49 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
50 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
51 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
52 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
53 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
54 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
55 #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
56 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
57 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000
58 #define CONFIG_SYS_FSL_MC_SIZE 0x4000000
59 #define CONFIG_SYS_FSL_NI_BASE 0x810000000
60 #define CONFIG_SYS_FSL_NI_SIZE 0x8000000
61 #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
62 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
63 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
64 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
65 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
66 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
67 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
68 #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
69 #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
70 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
71 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
72 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
73 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
74 #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
75 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
78 struct sys_mmu_table {
92 static const struct sys_mmu_table early_mmu_table[] = {
93 #ifdef CONFIG_FSL_LSCH3
94 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
95 CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
96 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
97 CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
98 /* For IFC Region #1, only the first 4MB is cache-enabled */
99 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
100 CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
101 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
102 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
103 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
104 MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
105 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
106 CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
107 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
108 CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
109 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
110 CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
111 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
112 CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
116 static const struct sys_mmu_table final_mmu_table[] = {
117 #ifdef CONFIG_FSL_LSCH3
118 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
119 CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
120 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
121 CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
122 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
123 CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
124 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
125 CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
126 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
127 CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
128 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
129 CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
130 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
131 CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
132 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
133 CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
134 /* For QBMAN portal, only the first 64MB is cache-enabled */
135 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
136 CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
137 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
138 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
139 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
140 MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
141 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
142 CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
143 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
144 CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
145 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
146 CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
147 #ifdef CONFIG_LS2085A
148 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
149 CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
151 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
152 CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
153 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
154 CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
155 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
156 CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
157 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
158 CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
163 int fsl_qoriq_core_to_cluster(unsigned int core);
165 #endif /* _FSL_LAYERSCAPE_CPU_H */