1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2014-2015, Freescale Semiconductor
7 #ifndef _FSL_LAYERSCAPE_CPU_H
8 #define _FSL_LAYERSCAPE_CPU_H
10 static struct cpu_type cpu_type_list[] = {
11 CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
12 CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
13 CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
14 CPU_TYPE_ENTRY(LS2088A, LS2088A, 8),
15 CPU_TYPE_ENTRY(LS2084A, LS2084A, 8),
16 CPU_TYPE_ENTRY(LS2048A, LS2048A, 4),
17 CPU_TYPE_ENTRY(LS2044A, LS2044A, 4),
18 CPU_TYPE_ENTRY(LS2081A, LS2081A, 8),
19 CPU_TYPE_ENTRY(LS2041A, LS2041A, 4),
20 CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
21 CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
22 CPU_TYPE_ENTRY(LS1046A, LS1046A, 4),
23 CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
24 CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
25 CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
26 CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
27 CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
28 CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
29 CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
32 #ifndef CONFIG_SYS_DCACHE_OFF
34 #ifdef CONFIG_FSL_LSCH3
35 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
36 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
37 #define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
38 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
39 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
40 #define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
41 #define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
42 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
43 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
44 #define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
45 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
46 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
47 #define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
48 #define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
49 #define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
50 #define CONFIG_SYS_FSL_MC_BASE 0x80c000000
51 #define CONFIG_SYS_FSL_MC_SIZE 0x4000000
52 #define CONFIG_SYS_FSL_NI_BASE 0x810000000
53 #define CONFIG_SYS_FSL_NI_SIZE 0x8000000
54 #define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
55 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
56 #define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
57 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
58 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
59 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
60 #define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
61 #define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
62 #define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
63 #define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
64 #define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
65 #define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
66 #define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
67 #define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
68 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
69 #elif defined(CONFIG_FSL_LSCH2)
70 #define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
71 #define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
72 #define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
73 #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
74 #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
75 #define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
76 #define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
77 #define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
78 #define CONFIG_SYS_FSL_IFC_BASE 0x60000000
79 #define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
80 #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
81 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
82 #define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
83 #define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
84 #define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
85 #define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
86 #define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
87 #define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
88 #define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
89 #define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
90 #define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
93 #define EARLY_PGTABLE_SIZE 0x5000
94 static struct mm_region early_map[] = {
95 #ifdef CONFIG_FSL_LSCH3
96 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
97 CONFIG_SYS_FSL_CCSR_SIZE,
98 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
99 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
101 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
102 SYS_FSL_OCRAM_SPACE_SIZE,
103 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
105 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
106 CONFIG_SYS_FSL_QSPI_SIZE1,
107 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
108 #ifdef CONFIG_FSL_IFC
109 /* For IFC Region #1, only the first 4MB is cache-enabled */
110 { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
111 CONFIG_SYS_FSL_IFC_SIZE1_1,
112 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
114 { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
115 CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
116 CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
117 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
119 { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
120 CONFIG_SYS_FSL_IFC_SIZE1,
121 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
124 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
125 CONFIG_SYS_FSL_DRAM_SIZE1,
126 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
127 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
128 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
129 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
131 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
133 #ifdef CONFIG_FSL_IFC
134 /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
135 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
136 CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
137 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
140 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
141 CONFIG_SYS_FSL_DCSR_SIZE,
142 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
143 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
145 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
146 CONFIG_SYS_FSL_DRAM_SIZE2,
147 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
148 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
150 #elif defined(CONFIG_FSL_LSCH2)
151 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
152 CONFIG_SYS_FSL_CCSR_SIZE,
153 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
154 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
156 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
157 SYS_FSL_OCRAM_SPACE_SIZE,
158 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
160 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
161 CONFIG_SYS_FSL_DCSR_SIZE,
162 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
163 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
165 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
166 CONFIG_SYS_FSL_QSPI_SIZE,
167 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
169 #ifdef CONFIG_FSL_IFC
170 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
171 CONFIG_SYS_FSL_IFC_SIZE,
172 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
175 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
176 CONFIG_SYS_FSL_DRAM_SIZE1,
177 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
178 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
179 #else /* Start with nGnRnE and PXN and UXN to prevent speculative access */
180 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
182 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
184 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
185 CONFIG_SYS_FSL_DRAM_SIZE2,
186 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
187 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
190 {}, /* list terminator */
193 static struct mm_region final_map[] = {
194 #ifdef CONFIG_FSL_LSCH3
195 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
196 CONFIG_SYS_FSL_CCSR_SIZE,
197 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
198 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
200 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
201 SYS_FSL_OCRAM_SPACE_SIZE,
202 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
204 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
205 CONFIG_SYS_FSL_DRAM_SIZE1,
206 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
207 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
209 { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
210 CONFIG_SYS_FSL_QSPI_SIZE1,
211 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
212 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
214 { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
215 CONFIG_SYS_FSL_QSPI_SIZE2,
216 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
217 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
219 #ifdef CONFIG_FSL_IFC
220 { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
221 CONFIG_SYS_FSL_IFC_SIZE2,
222 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
223 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
226 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
227 CONFIG_SYS_FSL_DCSR_SIZE,
228 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
229 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
231 { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
232 CONFIG_SYS_FSL_MC_SIZE,
233 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
234 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
236 { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
237 CONFIG_SYS_FSL_NI_SIZE,
238 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
239 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
241 /* For QBMAN portal, only the first 64MB is cache-enabled */
242 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
243 CONFIG_SYS_FSL_QBMAN_SIZE_1,
244 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
245 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS
247 { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
248 CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
249 CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
250 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
251 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
253 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
254 CONFIG_SYS_PCIE1_PHYS_SIZE,
255 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
256 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
258 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
259 CONFIG_SYS_PCIE2_PHYS_SIZE,
260 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
261 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
263 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
264 CONFIG_SYS_PCIE3_PHYS_SIZE,
265 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
266 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
268 #ifdef CONFIG_ARCH_LS2080A
269 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
270 CONFIG_SYS_PCIE4_PHYS_SIZE,
271 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
272 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
275 { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
276 CONFIG_SYS_FSL_WRIOP1_SIZE,
277 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
278 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
280 { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
281 CONFIG_SYS_FSL_AIOP1_SIZE,
282 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
283 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
285 { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
286 CONFIG_SYS_FSL_PEBUF_SIZE,
287 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
288 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
290 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
291 CONFIG_SYS_FSL_DRAM_SIZE2,
292 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
293 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
295 #elif defined(CONFIG_FSL_LSCH2)
296 { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
297 CONFIG_SYS_FSL_BOOTROM_SIZE,
298 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
299 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
301 { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
302 CONFIG_SYS_FSL_CCSR_SIZE,
303 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
304 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
306 { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
307 SYS_FSL_OCRAM_SPACE_SIZE,
308 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
310 { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
311 CONFIG_SYS_FSL_DCSR_SIZE,
312 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
313 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
315 { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
316 CONFIG_SYS_FSL_QSPI_SIZE,
317 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
318 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
320 #ifdef CONFIG_FSL_IFC
321 { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
322 CONFIG_SYS_FSL_IFC_SIZE,
323 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
326 { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
327 CONFIG_SYS_FSL_DRAM_SIZE1,
328 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
329 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
331 { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
332 CONFIG_SYS_FSL_QBMAN_SIZE,
333 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
334 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
336 { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
337 CONFIG_SYS_FSL_DRAM_SIZE2,
338 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
339 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
341 { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
342 CONFIG_SYS_PCIE1_PHYS_SIZE,
343 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
344 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
346 { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
347 CONFIG_SYS_PCIE2_PHYS_SIZE,
348 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
349 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
351 { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
352 CONFIG_SYS_PCIE3_PHYS_SIZE,
353 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
354 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
356 { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
357 CONFIG_SYS_FSL_DRAM_SIZE3,
358 PTE_BLOCK_MEMTYPE(MT_NORMAL) |
359 PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
362 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
363 {}, /* space holder for secure mem */
367 #endif /* !CONFIG_SYS_DCACHE_OFF */
369 int fsl_qoriq_core_to_cluster(unsigned int core);
372 #endif /* _FSL_LAYERSCAPE_CPU_H */