git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h

   1 /*
   2  * Copyright 2013-2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__
   8 #define __ARCH_FSL_LSCH2_IMMAP_H__
   9
  10 #include <fsl_immap.h>
  11
  12 #define CONFIG_SYS_IMMR                         0x01000000
  13 #define CONFIG_SYS_DCSRBAR                      0x20000000
  14 #define CONFIG_SYS_DCSR_DCFG_ADDR       (CONFIG_SYS_DCSRBAR + 0x00140000)
  15 #define CONFIG_SYS_DCSR_COP_CCP_ADDR    (CONFIG_SYS_DCSRBAR + 0x02008040)
  16
  17 #define CONFIG_SYS_FSL_DDR_ADDR                 (CONFIG_SYS_IMMR + 0x00080000)
  18 #define CONFIG_SYS_CCI400_ADDR                  (CONFIG_SYS_IMMR + 0x00180000)
  19 #define CONFIG_SYS_GIC400_ADDR                  (CONFIG_SYS_IMMR + 0x00400000)
  20 #define CONFIG_SYS_IFC_ADDR                     (CONFIG_SYS_IMMR + 0x00530000)
  21 #define CONFIG_SYS_FSL_ESDHC_ADDR               (CONFIG_SYS_IMMR + 0x00560000)
  22 #define CONFIG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
  23 #define CONFIG_SYS_FSL_GUTS_ADDR                (CONFIG_SYS_IMMR + 0x00ee0000)
  24 #define CONFIG_SYS_FSL_RST_ADDR                 (CONFIG_SYS_IMMR + 0x00ee00b0)
  25 #define CONFIG_SYS_FSL_SCFG_ADDR                (CONFIG_SYS_IMMR + 0x00570000)
  26 #define CONFIG_SYS_FSL_FMAN_ADDR                (CONFIG_SYS_IMMR + 0x00a00000)
  27 #define CONFIG_SYS_FSL_SERDES_ADDR              (CONFIG_SYS_IMMR + 0x00ea0000)
  28 #define CONFIG_SYS_FSL_DCFG_ADDR                (CONFIG_SYS_IMMR + 0x00ee0000)
  29 #define CONFIG_SYS_FSL_CLK_ADDR                 (CONFIG_SYS_IMMR + 0x00ee1000)
  30 #define CONFIG_SYS_NS16550_COM1                 (CONFIG_SYS_IMMR + 0x011c0500)
  31 #define CONFIG_SYS_NS16550_COM2                 (CONFIG_SYS_IMMR + 0x011c0600)
  32 #define CONFIG_SYS_NS16550_COM3                 (CONFIG_SYS_IMMR + 0x011d0500)
  33 #define CONFIG_SYS_NS16550_COM4                 (CONFIG_SYS_IMMR + 0x011d0600)
  34 #define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR       (CONFIG_SYS_IMMR + 0x01f00000)
  35 #define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR       (CONFIG_SYS_IMMR + 0x02000000)
  36 #define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR       (CONFIG_SYS_IMMR + 0x02100000)
  37 #define CONFIG_SYS_PCIE1_ADDR                   (CONFIG_SYS_IMMR + 0x2400000)
  38 #define CONFIG_SYS_PCIE2_ADDR                   (CONFIG_SYS_IMMR + 0x2500000)
  39 #define CONFIG_SYS_PCIE3_ADDR                   (CONFIG_SYS_IMMR + 0x2600000)
  40 #define CONFIG_SYS_SEC_MON_ADDR                 (CONFIG_SYS_IMMR + 0xe90000)
  41 #define CONFIG_SYS_SFP_ADDR                     (CONFIG_SYS_IMMR + 0xe80200)
  42
  43 #define CONFIG_SYS_FSL_TIMER_ADDR               0x02b00000
  44
  45 #define I2C1_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01180000)
  46 #define I2C2_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x01190000)
  47 #define I2C3_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x011a0000)
  48 #define I2C4_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x011b0000)
  49
  50 #define WDOG1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01ad0000)
  51
  52 #define QSPI0_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x00550000)
  53 #define DSPI1_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01100000)
  54
  55 #define LPUART_BASE                             (CONFIG_SYS_IMMR + 0x01950000)
  56
  57 #define AHCI_BASE_ADDR                          (CONFIG_SYS_IMMR + 0x02200000)
  58
  59 #define CONFIG_SYS_PCIE1_PHYS_ADDR              0x4000000000ULL
  60 #define CONFIG_SYS_PCIE2_PHYS_ADDR              0x4800000000ULL
  61 #define CONFIG_SYS_PCIE3_PHYS_ADDR              0x5000000000ULL
  62 /* LUT registers */
  63 #define PCIE_LUT_BASE                           0x10000
  64 #define PCIE_LUT_LCTRL0                         0x7F8
  65 #define PCIE_LUT_DBG                            0x7FC
  66
  67 /* TZ Address Space Controller Definitions */
  68 #define TZASC1_BASE                     0x01100000      /* as per CCSR map. */
  69 #define TZASC2_BASE                     0x01110000      /* as per CCSR map. */
  70 #define TZASC3_BASE                     0x01120000      /* as per CCSR map. */
  71 #define TZASC4_BASE                     0x01130000      /* as per CCSR map. */
  72 #define TZASC_BUILD_CONFIG_REG(x)       ((TZASC1_BASE + (x * 0x10000)))
  73 #define TZASC_ACTION_REG(x)             ((TZASC1_BASE + (x * 0x10000)) + 0x004)
  74 #define TZASC_GATE_KEEPER(x)            ((TZASC1_BASE + (x * 0x10000)) + 0x008)
  75 #define TZASC_REGION_BASE_LOW_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x100)
  76 #define TZASC_REGION_BASE_HIGH_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x104)
  77 #define TZASC_REGION_TOP_LOW_0(x)       ((TZASC1_BASE + (x * 0x10000)) + 0x108)
  78 #define TZASC_REGION_TOP_HIGH_0(x)      ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
  79 #define TZASC_REGION_ATTRIBUTES_0(x)    ((TZASC1_BASE + (x * 0x10000)) + 0x110)
  80 #define TZASC_REGION_ID_ACCESS_0(x)     ((TZASC1_BASE + (x * 0x10000)) + 0x114)
  81
  82 #define TP_ITYP_AV              0x00000001      /* Initiator available */
  83 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)      /* Initiator Type */
  84 #define TP_ITYP_TYPE_ARM        0x0
  85 #define TP_ITYP_TYPE_PPC        0x1             /* PowerPC */
  86 #define TP_ITYP_TYPE_OTHER      0x2             /* StarCore DSP */
  87 #define TP_ITYP_TYPE_HA         0x3             /* HW Accelerator */
  88 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)     /* # threads */
  89 #define TP_ITYP_VER(x)  (((x) & 0xe0) >> 5)     /* Initiator Version */
  90 #define TY_ITYP_VER_A7          0x1
  91 #define TY_ITYP_VER_A53         0x2
  92 #define TY_ITYP_VER_A57         0x3
  93
  94 #define TP_CLUSTER_EOC          0xc0000000      /* end of clusters */
  95 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
  96 #define TP_INIT_PER_CLUSTER     4
  97
  98 /*
  99  * Define default values for some CCSR macros to make header files cleaner*
 100  *
 101  * To completely disable CCSR relocation in a board header file, define
 102  * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
 103  * to a value that is the same as CONFIG_SYS_CCSRBAR.
 104  */
 105
 106 #ifdef CONFIG_SYS_CCSRBAR_PHYS
 107 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly.  Use \
 108 CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
 109 #endif
 110
 111 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 112 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
 113 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
 114 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0
 115 #endif
 116
 117 #ifndef CONFIG_SYS_CCSRBAR
 118 #define CONFIG_SYS_CCSRBAR              CONFIG_SYS_CCSRBAR_DEFAULT
 119 #endif
 120
 121 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
 122 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0
 123 #endif
 124
 125 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
 126 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR_DEFAULT
 127 #endif
 128
 129 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
 130                                  CONFIG_SYS_CCSRBAR_PHYS_LOW)
 131
 132 struct sys_info {
 133         unsigned long freq_processor[CONFIG_MAX_CPUS];
 134         unsigned long freq_systembus;
 135         unsigned long freq_ddrbus;
 136         unsigned long freq_localbus;
 137         unsigned long freq_sdhc;
 138 #ifdef CONFIG_SYS_DPAA_FMAN
 139         unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
 140 #endif
 141         unsigned long freq_qman;
 142 };
 143
 144 #define CONFIG_SYS_FSL_FM1_OFFSET               0xa00000
 145 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET        0xa88000
 146 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET        0xa89000
 147 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET        0xa8a000
 148 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET        0xa8b000
 149 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET        0xa8c000
 150 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET        0xa8d000
 151
 152 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET        0xae0000
 153 #define CONFIG_SYS_FSL_FM1_ADDR                 \
 154                 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
 155 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR          \
 156                 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 157
 158 #define CONFIG_SYS_FSL_SEC_OFFSET               0x700000ull
 159 #define CONFIG_SYS_FSL_JR0_OFFSET               0x710000ull
 160 #define CONFIG_SYS_FSL_SEC_ADDR \
 161         (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 162 #define CONFIG_SYS_FSL_JR0_ADDR \
 163         (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 164
 165 /* Device Configuration and Pin Control */
 166 struct ccsr_gur {
 167         u32     porsr1;         /* POR status 1 */
 168 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK       0xFF800000
 169         u32     porsr2;         /* POR status 2 */
 170         u8      res_008[0x20-0x8];
 171         u32     gpporcr1;       /* General-purpose POR configuration */
 172         u32     gpporcr2;
 173 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT      25
 174 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK       0x1F
 175 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT   20
 176 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK    0x1F
 177         u32     dcfg_fusesr;    /* Fuse status register */
 178         u8      res_02c[0x70-0x2c];
 179         u32     devdisr;        /* Device disable control */
 180 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1  0x80000000
 181 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2  0x40000000
 182 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3  0x20000000
 183 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4  0x10000000
 184 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5  0x08000000
 185 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6  0x04000000
 186 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9  0x00800000
 187 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10 0x00400000
 188 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1  0x00800000
 189 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2  0x00400000
 190 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3  0x80000000
 191 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4  0x40000000
 192         u32     devdisr2;       /* Device disable control 2 */
 193         u32     devdisr3;       /* Device disable control 3 */
 194         u32     devdisr4;       /* Device disable control 4 */
 195         u32     devdisr5;       /* Device disable control 5 */
 196         u32     devdisr6;       /* Device disable control 6 */
 197         u32     devdisr7;       /* Device disable control 7 */
 198         u8      res_08c[0x94-0x8c];
 199         u32     coredisru;      /* uppper portion for support of 64 cores */
 200         u32     coredisrl;      /* lower portion for support of 64 cores */
 201         u8      res_09c[0xa0-0x9c];
 202         u32     pvr;            /* Processor version */
 203         u32     svr;            /* System version */
 204         u32     mvr;            /* Manufacturing version */
 205         u8      res_0ac[0xb0-0xac];
 206         u32     rstcr;          /* Reset control */
 207         u32     rstrqpblsr;     /* Reset request preboot loader status */
 208         u8      res_0b8[0xc0-0xb8];
 209         u32     rstrqmr1;       /* Reset request mask */
 210         u8      res_0c4[0xc8-0xc4];
 211         u32     rstrqsr1;       /* Reset request status */
 212         u8      res_0cc[0xd4-0xcc];
 213         u32     rstrqwdtmrl;    /* Reset request WDT mask */
 214         u8      res_0d8[0xdc-0xd8];
 215         u32     rstrqwdtsrl;    /* Reset request WDT status */
 216         u8      res_0e0[0xe4-0xe0];
 217         u32     brrl;           /* Boot release */
 218         u8      res_0e8[0x100-0xe8];
 219         u32     rcwsr[16];      /* Reset control word status */
 220 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT   25
 221 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK    0x1f
 222 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT   16
 223 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK    0x3f
 224 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK    0xffff0000
 225 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT   16
 226 #define RCW_SB_EN_REG_INDEX     7
 227 #define RCW_SB_EN_MASK          0x00200000
 228
 229         u8      res_140[0x200-0x140];
 230         u32     scratchrw[4];  /* Scratch Read/Write */
 231         u8      res_210[0x300-0x210];
 232         u32     scratchw1r[4];  /* Scratch Read (Write once) */
 233         u8      res_310[0x400-0x310];
 234         u32     crstsr[12];
 235         u8      res_430[0x500-0x430];
 236
 237         /* PCI Express n Logical I/O Device Number register */
 238         u32 dcfg_ccsr_pex1liodnr;
 239         u32 dcfg_ccsr_pex2liodnr;
 240         u32 dcfg_ccsr_pex3liodnr;
 241         u32 dcfg_ccsr_pex4liodnr;
 242         /* RIO n Logical I/O Device Number register */
 243         u32 dcfg_ccsr_rio1liodnr;
 244         u32 dcfg_ccsr_rio2liodnr;
 245         u32 dcfg_ccsr_rio3liodnr;
 246         u32 dcfg_ccsr_rio4liodnr;
 247         /* USB Logical I/O Device Number register */
 248         u32 dcfg_ccsr_usb1liodnr;
 249         u32 dcfg_ccsr_usb2liodnr;
 250         u32 dcfg_ccsr_usb3liodnr;
 251         u32 dcfg_ccsr_usb4liodnr;
 252         /* SD/MMC Logical I/O Device Number register */
 253         u32 dcfg_ccsr_sdmmc1liodnr;
 254         u32 dcfg_ccsr_sdmmc2liodnr;
 255         u32 dcfg_ccsr_sdmmc3liodnr;
 256         u32 dcfg_ccsr_sdmmc4liodnr;
 257         /* RIO Message Unit Logical I/O Device Number register */
 258         u32 dcfg_ccsr_riomaintliodnr;
 259
 260         u8      res_544[0x550-0x544];
 261         u32     sataliodnr[4];
 262         u8      res_560[0x570-0x560];
 263
 264         u32 dcfg_ccsr_misc1liodnr;
 265         u32 dcfg_ccsr_misc2liodnr;
 266         u32 dcfg_ccsr_misc3liodnr;
 267         u32 dcfg_ccsr_misc4liodnr;
 268         u32 dcfg_ccsr_dma1liodnr;
 269         u32 dcfg_ccsr_dma2liodnr;
 270         u32 dcfg_ccsr_dma3liodnr;
 271         u32 dcfg_ccsr_dma4liodnr;
 272         u32 dcfg_ccsr_spare1liodnr;
 273         u32 dcfg_ccsr_spare2liodnr;
 274         u32 dcfg_ccsr_spare3liodnr;
 275         u32 dcfg_ccsr_spare4liodnr;
 276         u8      res_5a0[0x600-0x5a0];
 277         u32 dcfg_ccsr_pblsr;
 278
 279         u32     pamubypenr;
 280         u32     dmacr1;
 281
 282         u8      res_60c[0x610-0x60c];
 283         u32 dcfg_ccsr_gensr1;
 284         u32 dcfg_ccsr_gensr2;
 285         u32 dcfg_ccsr_gensr3;
 286         u32 dcfg_ccsr_gensr4;
 287         u32 dcfg_ccsr_gencr1;
 288         u32 dcfg_ccsr_gencr2;
 289         u32 dcfg_ccsr_gencr3;
 290         u32 dcfg_ccsr_gencr4;
 291         u32 dcfg_ccsr_gencr5;
 292         u32 dcfg_ccsr_gencr6;
 293         u32 dcfg_ccsr_gencr7;
 294         u8      res_63c[0x658-0x63c];
 295         u32 dcfg_ccsr_cgensr1;
 296         u32 dcfg_ccsr_cgensr0;
 297         u8      res_660[0x678-0x660];
 298         u32 dcfg_ccsr_cgencr1;
 299
 300         u32 dcfg_ccsr_cgencr0;
 301         u8      res_680[0x700-0x680];
 302         u32 dcfg_ccsr_sriopstecr;
 303         u32 dcfg_ccsr_dcsrcr;
 304
 305         u8      res_708[0x740-0x708];   /* add more registers when needed */
 306         u32     tp_ityp[64];    /* Topology Initiator Type Register */
 307         struct {
 308                 u32     upper;
 309                 u32     lower;
 310         } tp_cluster[16];
 311         u8      res_8c0[0xa00-0x8c0];   /* add more registers when needed */
 312         u32 dcfg_ccsr_qmbm_warmrst;
 313         u8      res_a04[0xa20-0xa04];   /* add more registers when needed */
 314         u32 dcfg_ccsr_reserved0;
 315         u32 dcfg_ccsr_reserved1;
 316 };
 317
 318 #define SCFG_QSPI_CLKSEL                0x40100000
 319 #define SCFG_USBDRVVBUS_SELCR_USB1      0x00000000
 320 #define SCFG_USBDRVVBUS_SELCR_USB2      0x00000001
 321 #define SCFG_USBDRVVBUS_SELCR_USB3      0x00000002
 322 #define SCFG_USBPWRFAULT_INACTIVE       0x00000000
 323 #define SCFG_USBPWRFAULT_SHARED         0x00000001
 324 #define SCFG_USBPWRFAULT_DEDICATED      0x00000002
 325 #define SCFG_USBPWRFAULT_USB3_SHIFT     4
 326 #define SCFG_USBPWRFAULT_USB2_SHIFT     2
 327 #define SCFG_USBPWRFAULT_USB1_SHIFT     0
 328
 329 #define SCFG_SNPCNFGCR_SECRDSNP         0x80000000
 330 #define SCFG_SNPCNFGCR_SECWRSNP         0x40000000
 331
 332 /* Supplemental Configuration Unit */
 333 struct ccsr_scfg {
 334         u8 res_000[0x100-0x000];
 335         u32 usb2_icid;
 336         u32 usb3_icid;
 337         u8 res_108[0x114-0x108];
 338         u32 dma_icid;
 339         u32 sata_icid;
 340         u32 usb1_icid;
 341         u32 qe_icid;
 342         u32 sdhc_icid;
 343         u32 edma_icid;
 344         u32 etr_icid;
 345         u32 core_sft_rst[4];
 346         u8 res_140[0x158-0x140];
 347         u32 altcbar;
 348         u32 qspi_cfg;
 349         u8 res_160[0x180-0x160];
 350         u32 dmamcr;
 351         u8 res_184[0x18c-0x184];
 352         u32 debug_icid;
 353         u8 res_190[0x1a4-0x190];
 354         u32 snpcnfgcr;
 355         u8 res_1a8[0x1ac-0x1a8];
 356         u32 intpcr;
 357         u8 res_1b0[0x204-0x1b0];
 358         u32 coresrencr;
 359         u8 res_208[0x220-0x208];
 360         u32 rvbar0_0;
 361         u32 rvbar0_1;
 362         u32 rvbar1_0;
 363         u32 rvbar1_1;
 364         u32 rvbar2_0;
 365         u32 rvbar2_1;
 366         u32 rvbar3_0;
 367         u32 rvbar3_1;
 368         u32 lpmcsr;
 369         u8 res_244[0x400-0x244];
 370         u32 qspidqscr;
 371         u32 ecgtxcmcr;
 372         u32 sdhciovselcr;
 373         u32 rcwpmuxcr0;
 374         u32 usbdrvvbus_selcr;
 375         u32 usbpwrfault_selcr;
 376         u32 usb_refclk_selcr1;
 377         u32 usb_refclk_selcr2;
 378         u32 usb_refclk_selcr3;
 379         u8 res_424[0x600-0x424];
 380         u32 scratchrw[4];
 381         u8 res_610[0x680-0x610];
 382         u32 corebcr;
 383         u8 res_684[0x1000-0x684];
 384         u32 pex1msiir;
 385         u32 pex1msir;
 386         u8 res_1008[0x2000-0x1008];
 387         u32 pex2;
 388         u32 pex2msir;
 389         u8 res_2008[0x3000-0x2008];
 390         u32 pex3msiir;
 391         u32 pex3msir;
 392 };
 393
 394 /* Clocking */
 395 struct ccsr_clk {
 396         struct {
 397                 u32 clkcncsr;   /* core cluster n clock control status */
 398                 u8  res_004[0x0c];
 399                 u32 clkcghwacsr; /* Clock generator n hardware accelerator */
 400                 u8  res_014[0x0c];
 401         } clkcsr[4];
 402         u8      res_040[0x780]; /* 0x100 */
 403         struct {
 404                 u32 pllcngsr;
 405                 u8 res_804[0x1c];
 406         } pllcgsr[2];
 407         u8      res_840[0x1c0];
 408         u32     clkpcsr;        /* 0xa00 Platform clock domain control/status */
 409         u8      res_a04[0x1fc];
 410         u32     pllpgsr;        /* 0xc00 Platform PLL General Status */
 411         u8      res_c04[0x1c];
 412         u32     plldgsr;        /* 0xc20 DDR PLL General Status */
 413         u8      res_c24[0x3dc];
 414 };
 415
 416 /* System Counter */
 417 struct sctr_regs {
 418         u32 cntcr;
 419         u32 cntsr;
 420         u32 cntcv1;
 421         u32 cntcv2;
 422         u32 resv1[4];
 423         u32 cntfid0;
 424         u32 cntfid1;
 425         u32 resv2[1002];
 426         u32 counterid[12];
 427 };
 428
 429 #define SRDS_MAX_LANES          4
 430 struct ccsr_serdes {
 431         struct {
 432                 u32     rstctl; /* Reset Control Register */
 433 #define SRDS_RSTCTL_RST         0x80000000
 434 #define SRDS_RSTCTL_RSTDONE     0x40000000
 435 #define SRDS_RSTCTL_RSTERR      0x20000000
 436 #define SRDS_RSTCTL_SWRST       0x10000000
 437 #define SRDS_RSTCTL_SDEN        0x00000020
 438 #define SRDS_RSTCTL_SDRST_B     0x00000040
 439 #define SRDS_RSTCTL_PLLRST_B    0x00000080
 440                 u32     pllcr0; /* PLL Control Register 0 */
 441 #define SRDS_PLLCR0_POFF                0x80000000
 442 #define SRDS_PLLCR0_RFCK_SEL_MASK       0x70000000
 443 #define SRDS_PLLCR0_RFCK_SEL_100        0x00000000
 444 #define SRDS_PLLCR0_RFCK_SEL_125        0x10000000
 445 #define SRDS_PLLCR0_RFCK_SEL_156_25     0x20000000
 446 #define SRDS_PLLCR0_RFCK_SEL_150        0x30000000
 447 #define SRDS_PLLCR0_RFCK_SEL_161_13     0x40000000
 448 #define SRDS_PLLCR0_RFCK_SEL_122_88     0x50000000
 449 #define SRDS_PLLCR0_PLL_LCK             0x00800000
 450 #define SRDS_PLLCR0_FRATE_SEL_MASK      0x000f0000
 451 #define SRDS_PLLCR0_FRATE_SEL_5         0x00000000
 452 #define SRDS_PLLCR0_FRATE_SEL_3_75      0x00050000
 453 #define SRDS_PLLCR0_FRATE_SEL_5_15      0x00060000
 454 #define SRDS_PLLCR0_FRATE_SEL_4         0x00070000
 455 #define SRDS_PLLCR0_FRATE_SEL_3_12      0x00090000
 456 #define SRDS_PLLCR0_FRATE_SEL_3         0x000a0000
 457                 u32     pllcr1; /* PLL Control Register 1 */
 458 #define SRDS_PLLCR1_PLL_BWSEL   0x08000000
 459                 u32     res_0c; /* 0x00c */
 460                 u32     pllcr3;
 461                 u32     pllcr4;
 462                 u32     pllcr5; /* 0x018 SerDes PLL1 Control 5 */
 463                 u8      res_1c[0x20-0x1c];
 464         } bank[2];
 465         u8      res_40[0x90-0x40];
 466         u32     srdstcalcr;     /* 0x90 TX Calibration Control */
 467         u8      res_94[0xa0-0x94];
 468         u32     srdsrcalcr;     /* 0xa0 RX Calibration Control */
 469         u8      res_a4[0xb0-0xa4];
 470         u32     srdsgr0;        /* 0xb0 General Register 0 */
 471         u8      res_b4[0x100-0xb4];
 472         struct {
 473                 u32     lnpssr0;        /* 0x100, 0x120, 0x140, 0x160 */
 474                 u8      res_104[0x120-0x104];
 475         } lnpssr[4];    /* Lane A, B, C, D */
 476         u8      res_180[0x200-0x180];
 477         u32     srdspccr0;      /* 0x200 Protocol Configuration 0 */
 478         u32     srdspccr1;      /* 0x204 Protocol Configuration 1 */
 479         u32     srdspccr2;      /* 0x208 Protocol Configuration 2 */
 480         u32     srdspccr3;      /* 0x20c Protocol Configuration 3 */
 481         u32     srdspccr4;      /* 0x210 Protocol Configuration 4 */
 482         u32     srdspccr5;      /* 0x214 Protocol Configuration 5 */
 483         u32     srdspccr6;      /* 0x218 Protocol Configuration 6 */
 484         u32     srdspccr7;      /* 0x21c Protocol Configuration 7 */
 485         u32     srdspccr8;      /* 0x220 Protocol Configuration 8 */
 486         u32     srdspccr9;      /* 0x224 Protocol Configuration 9 */
 487         u32     srdspccra;      /* 0x228 Protocol Configuration A */
 488         u32     srdspccrb;      /* 0x22c Protocol Configuration B */
 489         u8      res_230[0x800-0x230];
 490         struct {
 491                 u32     gcr0;   /* 0x800 General Control Register 0 */
 492                 u32     gcr1;   /* 0x804 General Control Register 1 */
 493                 u32     gcr2;   /* 0x808 General Control Register 2 */
 494                 u32     sscr0;
 495                 u32     recr0;  /* 0x810 Receive Equalization Control */
 496                 u32     recr1;
 497                 u32     tecr0;  /* 0x818 Transmit Equalization Control */
 498                 u32     sscr1;
 499                 u32     ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
 500                 u8      res_824[0x83c-0x824];
 501                 u32     tcsr3;
 502         } lane[4];      /* Lane A, B, C, D */
 503         u8      res_900[0x1000-0x900];  /* from 0x900 to 0xfff */
 504         struct {
 505                 u32     srdspexcr0;     /* 0x1000, 0x1040, 0x1080 */
 506                 u8      res_1004[0x1040-0x1004];
 507         } pcie[3];
 508         u8      res_10c0[0x1800-0x10c0];
 509         struct {
 510                 u8      res_1800[0x1804-0x1800];
 511                 u32     srdssgmiicr1;   /* 0x1804 SGMII Protocol Control 1 */
 512                 u8      res_1808[0x180c-0x1808];
 513                 u32     srdssgmiicr3;   /* 0x180c SGMII Protocol Control 3 */
 514         } sgmii[4];     /* Lane A, B, C, D */
 515         u8      res_1840[0x1880-0x1840];
 516         struct {
 517                 u8      res_1880[0x1884-0x1880];
 518                 u32     srdsqsgmiicr1;  /* 0x1884 QSGMII Protocol Control 1 */
 519                 u8      res_1888[0x188c-0x1888];
 520                 u32     srdsqsgmiicr3;  /* 0x188c QSGMII Protocol Control 3 */
 521         } qsgmii[2];    /* Lane A, B */
 522         u8      res_18a0[0x1980-0x18a0];
 523         struct {
 524                 u8      res_1980[0x1984-0x1980];
 525                 u32     srdsxficr1;     /* 0x1984 XFI Protocol Control 1 */
 526                 u8      res_1988[0x198c-0x1988];
 527                 u32     srdsxficr3;     /* 0x198c XFI Protocol Control 3 */
 528         } xfi[2];       /* Lane A, B */
 529         u8      res_19a0[0x2000-0x19a0];        /* from 0x19a0 to 0x1fff */
 530 };
 531
 532 #define CCI400_CTRLORD_TERM_BARRIER     0x00000008
 533 #define CCI400_CTRLORD_EN_BARRIER       0
 534 #define CCI400_SHAORD_NON_SHAREABLE     0x00000002
 535 #define CCI400_DVM_MESSAGE_REQ_EN       0x00000002
 536 #define CCI400_SNOOP_REQ_EN             0x00000001
 537
 538 /* CCI-400 registers */
 539 struct ccsr_cci400 {
 540         u32 ctrl_ord;                   /* Control Override */
 541         u32 spec_ctrl;                  /* Speculation Control */
 542         u32 secure_access;              /* Secure Access */
 543         u32 status;                     /* Status */
 544         u32 impr_err;                   /* Imprecise Error */
 545         u8 res_14[0x100 - 0x14];
 546         u32 pmcr;                       /* Performance Monitor Control */
 547         u8 res_104[0xfd0 - 0x104];
 548         u32 pid[8];                     /* Peripheral ID */
 549         u32 cid[4];                     /* Component ID */
 550         struct {
 551                 u32 snoop_ctrl;         /* Snoop Control */
 552                 u32 sha_ord;            /* Shareable Override */
 553                 u8 res_1008[0x1100 - 0x1008];
 554                 u32 rc_qos_ord;         /* read channel QoS Value Override */
 555                 u32 wc_qos_ord;         /* read channel QoS Value Override */
 556                 u8 res_1108[0x110c - 0x1108];
 557                 u32 qos_ctrl;           /* QoS Control */
 558                 u32 max_ot;             /* Max OT */
 559                 u8 res_1114[0x1130 - 0x1114];
 560                 u32 target_lat;         /* Target Latency */
 561                 u32 latency_regu;       /* Latency Regulation */
 562                 u32 qos_range;          /* QoS Range */
 563                 u8 res_113c[0x2000 - 0x113c];
 564         } slave[5];                     /* Slave Interface */
 565         u8 res_6000[0x9004 - 0x6000];
 566         u32 cycle_counter;              /* Cycle counter */
 567         u32 count_ctrl;                 /* Count Control */
 568         u32 overflow_status;            /* Overflow Flag Status */
 569         u8 res_9010[0xa000 - 0x9010];
 570         struct {
 571                 u32 event_select;       /* Event Select */
 572                 u32 event_count;        /* Event Count */
 573                 u32 counter_ctrl;       /* Counter Control */
 574                 u32 overflow_status;    /* Overflow Flag Status */
 575                 u8 res_a010[0xb000 - 0xa010];
 576         } pcounter[4];                  /* Performance Counter */
 577         u8 res_e004[0x10000 - 0xe004];
 578 };
 579
 580 /* MMU 500 */
 581 #define SMMU_SCR0                       (SMMU_BASE + 0x0)
 582 #define SMMU_SCR1                       (SMMU_BASE + 0x4)
 583 #define SMMU_SCR2                       (SMMU_BASE + 0x8)
 584 #define SMMU_SACR                       (SMMU_BASE + 0x10)
 585 #define SMMU_IDR0                       (SMMU_BASE + 0x20)
 586 #define SMMU_IDR1                       (SMMU_BASE + 0x24)
 587
 588 #define SMMU_NSCR0                      (SMMU_BASE + 0x400)
 589 #define SMMU_NSCR2                      (SMMU_BASE + 0x408)
 590 #define SMMU_NSACR                      (SMMU_BASE + 0x410)
 591
 592 #define SCR0_CLIENTPD_MASK              0x00000001
 593 #define SCR0_USFCFG_MASK                0x00000400
 594
 595 #endif  /* __ARCH_FSL_LSCH2_IMMAP_H__*/