2 * LayerScape Internal Memory Map
4 * Copyright (C) 2017 NXP Semiconductors
5 * Copyright 2014 Freescale Semiconductor, Inc.
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __ARCH_FSL_LSCH3_IMMAP_H_
11 #define __ARCH_FSL_LSCH3_IMMAP_H_
13 #define CONFIG_SYS_IMMR 0x01000000
14 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
15 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
16 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
17 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
18 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
19 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
20 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
21 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
22 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
23 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
24 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
25 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
26 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
27 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
28 #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
29 #define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000
30 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
32 #define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
33 #define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
35 #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
36 #define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
37 #define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
38 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
40 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
41 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
42 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
43 #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
45 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
46 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
47 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
48 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
49 #define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01330000)
50 #define GPIO4_GPDIR_ADDR (GPIO4_BASE_ADDR + 0x0)
51 #define GPIO4_GPDAT_ADDR (GPIO4_BASE_ADDR + 0x8)
53 #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
54 #define CONFIG_SYS_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
56 /* TZ Address Space Controller Definitions */
57 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */
58 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */
59 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */
60 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */
61 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
62 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
63 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
64 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
65 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
66 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
67 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
68 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
69 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
72 #define AHCI_BASE_ADDR1 (CONFIG_SYS_IMMR + 0x02200000)
73 #define AHCI_BASE_ADDR2 (CONFIG_SYS_IMMR + 0x02210000)
76 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
79 #define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
80 #define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
81 #define CONFIG_SYS_FSL_SEC_ADDR \
82 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
83 #define CONFIG_SYS_FSL_JR0_ADDR \
84 (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
86 /* Security Monitor */
87 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
90 #define SMMU_SCR0 (SMMU_BASE + 0x0)
91 #define SMMU_SCR1 (SMMU_BASE + 0x4)
92 #define SMMU_SCR2 (SMMU_BASE + 0x8)
93 #define SMMU_SACR (SMMU_BASE + 0x10)
94 #define SMMU_IDR0 (SMMU_BASE + 0x20)
95 #define SMMU_IDR1 (SMMU_BASE + 0x24)
97 #define SMMU_NSCR0 (SMMU_BASE + 0x400)
98 #define SMMU_NSCR2 (SMMU_BASE + 0x408)
99 #define SMMU_NSACR (SMMU_BASE + 0x410)
101 #define SCR0_CLIENTPD_MASK 0x00000001
102 #define SCR0_USFCFG_MASK 0x00000400
106 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
107 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
108 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
109 #define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
110 #ifdef CONFIG_ARCH_LS1088A
111 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
112 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
113 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
115 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
116 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
117 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
118 #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
121 /* Device Configuration */
122 #define DCFG_BASE 0x01e00000
123 #define DCFG_PORSR1 0x000
124 #define DCFG_PORSR1_RCW_SRC 0xff800000
125 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
126 #define DCFG_RCWSR13 0x130
127 #define DCFG_RCWSR13_DSPI (0 << 8)
128 #define DCFG_RCWSR15 0x138
129 #define DCFG_RCWSR15_IFCGRPABASE_QSPI 0x3
131 #define DCFG_DCSR_BASE 0X700100000ULL
132 #define DCFG_DCSR_PORCR1 0x000
134 /* Interrupt Sampling Control */
135 #define ISC_BASE 0x01F70000
136 #define IRQCR_OFFSET 0x14
138 /* Supplemental Configuration */
139 #define SCFG_BASE 0x01fc0000
140 #define SCFG_USB3PRM1CR 0x000
141 #define SCFG_USB3PRM1CR_INIT 0x27672b2a
142 #define SCFG_USB_TXVREFTUNE 0x9
143 #define SCFG_USB_SQRXTUNE_MASK 0x7
144 #define SCFG_QSPICLKCTLR 0x10
146 #define DCSR_BASE 0x700000000ULL
147 #define DCSR_USB_PHY1 0x4600000
148 #define DCSR_USB_PHY2 0x4610000
149 #define DCSR_USB_PHY_RX_OVRD_IN_HI 0x200C
150 #define USB_PHY_RX_EQ_VAL_1 0x0000
151 #define USB_PHY_RX_EQ_VAL_2 0x0080
152 #define USB_PHY_RX_EQ_VAL_3 0x0380
153 #define USB_PHY_RX_EQ_VAL_4 0x0b80
155 #define TP_ITYP_AV 0x00000001 /* Initiator available */
156 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1) /* Initiator Type */
157 #define TP_ITYP_TYPE_ARM 0x0
158 #define TP_ITYP_TYPE_PPC 0x1 /* PowerPC */
159 #define TP_ITYP_TYPE_OTHER 0x2 /* StarCore DSP */
160 #define TP_ITYP_TYPE_HA 0x3 /* HW Accelerator */
161 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3) /* # threads */
162 #define TP_ITYP_VER(x) (((x) & 0xe0) >> 5) /* Initiator Version */
163 #define TY_ITYP_VER_A7 0x1
164 #define TY_ITYP_VER_A53 0x2
165 #define TY_ITYP_VER_A57 0x3
166 #define TY_ITYP_VER_A72 0x4
168 #define TP_CLUSTER_EOC 0x80000000 /* end of clusters */
169 #define TP_CLUSTER_INIT_MASK 0x0000003f /* initiator mask */
170 #define TP_INIT_PER_CLUSTER 4
171 /* This is chassis generation 3 */
174 unsigned long freq_processor[CONFIG_MAX_CPUS];
175 /* frequency of platform PLL */
176 unsigned long freq_systembus;
177 unsigned long freq_ddrbus;
178 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
179 unsigned long freq_ddrbus2;
181 unsigned long freq_localbus;
182 unsigned long freq_qe;
183 #ifdef CONFIG_SYS_DPAA_FMAN
184 unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
186 #ifdef CONFIG_SYS_DPAA_QBMAN
187 unsigned long freq_qman;
189 #ifdef CONFIG_SYS_DPAA_PME
190 unsigned long freq_pme;
194 /* Global Utilities Block */
196 u32 porsr1; /* POR status 1 */
197 u32 porsr2; /* POR status 2 */
198 u8 res_008[0x20-0x8];
199 u32 gpporcr1; /* General-purpose POR configuration */
200 u32 gpporcr2; /* General-purpose POR configuration 2 */
203 u8 res_030[0x60-0x30];
204 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK 0x1F
205 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK 0x1F
206 #if defined(CONFIG_ARCH_LS1088A)
207 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 25
208 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 20
210 #define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT 2
211 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT 7
213 u32 dcfg_fusesr; /* Fuse status register */
214 u8 res_064[0x70-0x64];
215 u32 devdisr; /* Device disable control 1 */
216 u32 devdisr2; /* Device disable control 2 */
217 u32 devdisr3; /* Device disable control 3 */
218 u32 devdisr4; /* Device disable control 4 */
219 u32 devdisr5; /* Device disable control 5 */
220 u32 devdisr6; /* Device disable control 6 */
221 u8 res_088[0x94-0x88];
222 u32 coredisr; /* Device disable control 7 */
223 #define FSL_CHASSIS3_DEVDISR2_DPMAC1 0x00000001
224 #define FSL_CHASSIS3_DEVDISR2_DPMAC2 0x00000002
225 #define FSL_CHASSIS3_DEVDISR2_DPMAC3 0x00000004
226 #define FSL_CHASSIS3_DEVDISR2_DPMAC4 0x00000008
227 #define FSL_CHASSIS3_DEVDISR2_DPMAC5 0x00000010
228 #define FSL_CHASSIS3_DEVDISR2_DPMAC6 0x00000020
229 #define FSL_CHASSIS3_DEVDISR2_DPMAC7 0x00000040
230 #define FSL_CHASSIS3_DEVDISR2_DPMAC8 0x00000080
231 #define FSL_CHASSIS3_DEVDISR2_DPMAC9 0x00000100
232 #define FSL_CHASSIS3_DEVDISR2_DPMAC10 0x00000200
233 #define FSL_CHASSIS3_DEVDISR2_DPMAC11 0x00000400
234 #define FSL_CHASSIS3_DEVDISR2_DPMAC12 0x00000800
235 #define FSL_CHASSIS3_DEVDISR2_DPMAC13 0x00001000
236 #define FSL_CHASSIS3_DEVDISR2_DPMAC14 0x00002000
237 #define FSL_CHASSIS3_DEVDISR2_DPMAC15 0x00004000
238 #define FSL_CHASSIS3_DEVDISR2_DPMAC16 0x00008000
239 #define FSL_CHASSIS3_DEVDISR2_DPMAC17 0x00010000
240 #define FSL_CHASSIS3_DEVDISR2_DPMAC18 0x00020000
241 #define FSL_CHASSIS3_DEVDISR2_DPMAC19 0x00040000
242 #define FSL_CHASSIS3_DEVDISR2_DPMAC20 0x00080000
243 #define FSL_CHASSIS3_DEVDISR2_DPMAC21 0x00100000
244 #define FSL_CHASSIS3_DEVDISR2_DPMAC22 0x00200000
245 #define FSL_CHASSIS3_DEVDISR2_DPMAC23 0x00400000
246 #define FSL_CHASSIS3_DEVDISR2_DPMAC24 0x00800000
247 u8 res_098[0xa0-0x98];
248 u32 pvr; /* Processor version */
249 u32 svr; /* System version */
250 u8 res_0a8[0x100-0xa8];
251 u32 rcwsr[30]; /* Reset control word status */
253 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_SHIFT 2
254 #define FSL_CHASSIS3_RCWSR0_SYS_PLL_RAT_MASK 0x1f
255 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT 10
256 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK 0x3f
257 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
258 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK 0x3f
260 #if defined(CONFIG_ARCH_LS2080A)
261 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK 0x00FF0000
262 #define FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT 16
263 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK 0xFF000000
264 #define FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT 24
265 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
266 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
267 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
268 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
269 #define FSL_CHASSIS3_SRDS1_REGSR 29
270 #define FSL_CHASSIS3_SRDS2_REGSR 29
271 #elif defined(CONFIG_ARCH_LS1088A)
272 #define FSL_CHASSIS3_EC1_REGSR 26
273 #define FSL_CHASSIS3_EC2_REGSR 26
274 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_MASK 0x00000007
275 #define FSL_CHASSIS3_RCWSR25_EC1_PRTCL_SHIFT 0
276 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_MASK 0x00000038
277 #define FSL_CHASSIS3_RCWSR25_EC2_PRTCL_SHIFT 3
278 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK 0xFFFF0000
279 #define FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT 16
280 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK 0x0000FFFF
281 #define FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT 0
282 #define FSL_CHASSIS3_SRDS1_PRTCL_MASK FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
283 #define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
284 #define FSL_CHASSIS3_SRDS2_PRTCL_MASK FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
285 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
286 #define FSL_CHASSIS3_SRDS1_REGSR 29
287 #define FSL_CHASSIS3_SRDS2_REGSR 30
289 #define RCW_SB_EN_REG_INDEX 9
290 #define RCW_SB_EN_MASK 0x00000400
292 u8 res_178[0x200-0x178];
293 u32 scratchrw[16]; /* Scratch Read/Write */
294 u8 res_240[0x300-0x240];
295 u32 scratchw1r[4]; /* Scratch Read (Write once) */
296 u8 res_310[0x400-0x310];
297 u32 bootlocptrl; /* Boot location pointer low-order addr */
298 u32 bootlocptrh; /* Boot location pointer high-order addr */
299 u8 res_408[0x520-0x408];
302 u8 res_528[0x530-0x528]; /* add more registers when needed */
304 u8 res_534[0x550-0x534]; /* add more registers when needed */
307 u8 res_558[0x570-0x558]; /* add more registers when needed */
309 u8 res_574[0x590-0x574]; /* add more registers when needed */
312 u8 res_598[0x620-0x598]; /* add more registers when needed */
313 u32 gencr[7]; /* General Control Registers */
314 u8 res_63c[0x640-0x63c]; /* add more registers when needed */
315 u32 cgensr1; /* Core General Status Register */
316 u8 res_644[0x660-0x644]; /* add more registers when needed */
317 u32 cgencr1; /* Core General Control Register */
318 u8 res_664[0x740-0x664]; /* add more registers when needed */
319 u32 tp_ityp[64]; /* Topology Initiator Type Register */
323 } tp_cluster[4]; /* Core cluster n Topology Register */
324 u8 res_864[0x920-0x864]; /* add more registers when needed */
325 u32 ioqoscr[8]; /*I/O Quality of Services Register */
327 u8 res_944[0x960-0x944]; /* add more registers when needed */
329 u8 res_964[0x990-0x964]; /* add more registers when needed */
331 u8 res_994[0xa00-0x994]; /* add more registers when needed */
332 u32 sdbgcr; /*Secure Debug Confifuration Register */
333 u8 res_a04[0xbf8-0xa04]; /* add more registers when needed */
336 u8 res_858[0x1000-0xc00];
339 struct ccsr_clk_cluster_group {
343 u8 res_14[0x20-0x14];
345 u8 res_60[0x80-0x60];
348 u8 res_84[0xa0-0x84];
350 u8 res_e0[0x100-0xe0];
353 struct ccsr_clk_ctrl {
355 u32 csr; /* core cluster n clock control status */
356 u8 res_04[0x20-0x04];
361 u32 rstcr; /* 0x000 */
362 u32 rstcrsp; /* 0x004 */
363 u8 res_008[0x10-0x08]; /* 0x008 */
364 u32 rstrqmr1; /* 0x010 */
365 u32 rstrqmr2; /* 0x014 */
366 u32 rstrqsr1; /* 0x018 */
367 u32 rstrqsr2; /* 0x01c */
368 u32 rstrqwdtmrl; /* 0x020 */
369 u32 rstrqwdtmru; /* 0x024 */
370 u8 res_028[0x30-0x28]; /* 0x028 */
371 u32 rstrqwdtsrl; /* 0x030 */
372 u32 rstrqwdtsru; /* 0x034 */
373 u8 res_038[0x60-0x38]; /* 0x038 */
374 u32 brrl; /* 0x060 */
375 u32 brru; /* 0x064 */
376 u8 res_068[0x80-0x68]; /* 0x068 */
377 u32 pirset; /* 0x080 */
378 u32 pirclr; /* 0x084 */
379 u8 res_088[0x90-0x88]; /* 0x088 */
380 u32 brcorenbr; /* 0x090 */
381 u8 res_094[0x100-0x94]; /* 0x094 */
382 u32 rcw_reqr; /* 0x100 */
383 u32 rcw_completion; /* 0x104 */
384 u8 res_108[0x110-0x108]; /* 0x108 */
385 u32 pbi_reqr; /* 0x110 */
386 u32 pbi_completion; /* 0x114 */
387 u8 res_118[0xa00-0x118]; /* 0x118 */
388 u32 qmbm_warmrst; /* 0xa00 */
389 u32 soc_warmrst; /* 0xa04 */
390 u8 res_a08[0xbf8-0xa08]; /* 0xa08 */
391 u32 ip_rev1; /* 0xbf8 */
392 u32 ip_rev2; /* 0xbfc */
397 u32 rstctl; /* Reset Control Register */
398 u32 pllcr0; /* PLL Control Register 0 */
399 u32 pllcr1; /* PLL Control Register 1 */
400 u32 pllcr2; /* PLL Control Register 2 */
401 u32 pllcr3; /* PLL Control Register 3 */
402 u32 pllcr4; /* PLL Control Register 4 */
403 u32 pllcr5; /* PLL Control Register 5 */
406 u8 res1[0x90 - 0x40];
407 u32 srdstcalcr; /* TX Calibration Control */
408 u32 srdstcalcr1; /* TX Calibration Control1 */
409 u8 res2[0xa0 - 0x98];
410 u32 srdsrcalcr; /* RX Calibration Control */
411 u32 srdsrcalcr1; /* RX Calibration Control1 */
412 u8 res3[0xb0 - 0xa8];
413 u32 srdsgr0; /* General Register 0 */
414 u8 res4[0x800 - 0xb4];
416 u32 gcr0; /* General Control Register 0 */
417 u32 gcr1; /* General Control Register 1 */
418 u32 gcr2; /* General Control Register 2 */
419 u32 ssc0; /* Speed Switch Control 0 */
420 u32 rec0; /* Receive Equalization Control 0 */
421 u32 rec1; /* Receive Equalization Control 1 */
422 u32 tec0; /* Transmit Equalization Control 0 */
423 u32 ssc1; /* Speed Switch Control 1 */
424 u8 res1[0x840 - 0x820];
426 u8 res5[0x19fc - 0xa00];
429 #endif /*__ASSEMBLY__*/
430 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */