2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __FSL_NS_ACCESS_H_
8 #define __FSL_NS_ACCESS_H_
11 CSU_CSLX_PCIE2_IO = 0,
23 CSU_CSLX_QM_BM_SWPORTAL,
53 CSU_CSLX_DCFG_CCU_RCPM = 60,
54 CSU_CSLX_SECURE_BOOTROM,
57 CSU_CSLX_SECURE_MONITOR,
67 CSU_CSLX_PLATFORM_CONT,
84 static struct csu_ns_dev ns_dev[] = {
85 {CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
86 {CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
87 {CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
88 {CSU_CSLX_IFC_MEM, CSU_ALL_RW},
89 {CSU_CSLX_OCRAM, CSU_ALL_RW},
90 {CSU_CSLX_GIC, CSU_ALL_RW},
91 {CSU_CSLX_PCIE1, CSU_ALL_RW},
92 {CSU_CSLX_OCRAM2, CSU_ALL_RW},
93 {CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
94 {CSU_CSLX_PCIE2, CSU_ALL_RW},
95 {CSU_CSLX_SATA, CSU_ALL_RW},
96 {CSU_CSLX_USB1, CSU_ALL_RW},
97 {CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
98 {CSU_CSLX_PCIE3, CSU_ALL_RW},
99 {CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
100 {CSU_CSLX_USB3, CSU_ALL_RW},
101 {CSU_CSLX_USB2, CSU_ALL_RW},
102 {CSU_CSLX_SERDES, CSU_ALL_RW},
103 {CSU_CSLX_QDMA, CSU_ALL_RW},
104 {CSU_CSLX_LPUART2, CSU_ALL_RW},
105 {CSU_CSLX_LPUART1, CSU_ALL_RW},
106 {CSU_CSLX_LPUART4, CSU_ALL_RW},
107 {CSU_CSLX_LPUART3, CSU_ALL_RW},
108 {CSU_CSLX_LPUART6, CSU_ALL_RW},
109 {CSU_CSLX_LPUART5, CSU_ALL_RW},
110 {CSU_CSLX_DSPI1, CSU_ALL_RW},
111 {CSU_CSLX_QSPI, CSU_ALL_RW},
112 {CSU_CSLX_ESDHC, CSU_ALL_RW},
113 {CSU_CSLX_IFC, CSU_ALL_RW},
114 {CSU_CSLX_I2C1, CSU_ALL_RW},
115 {CSU_CSLX_I2C3, CSU_ALL_RW},
116 {CSU_CSLX_I2C2, CSU_ALL_RW},
117 {CSU_CSLX_DUART2, CSU_ALL_RW},
118 {CSU_CSLX_DUART1, CSU_ALL_RW},
119 {CSU_CSLX_WDT2, CSU_ALL_RW},
120 {CSU_CSLX_WDT1, CSU_ALL_RW},
121 {CSU_CSLX_EDMA, CSU_ALL_RW},
122 {CSU_CSLX_SYS_CNT, CSU_ALL_RW},
123 {CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
124 {CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
125 {CSU_CSLX_DDR, CSU_ALL_RW},
126 {CSU_CSLX_QUICC, CSU_ALL_RW},
127 {CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
128 {CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
129 {CSU_CSLX_SFP, CSU_ALL_RW},
130 {CSU_CSLX_TMU, CSU_ALL_RW},
131 {CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
132 {CSU_CSLX_SCFG, CSU_ALL_RW},
133 {CSU_CSLX_FM, CSU_ALL_RW},
134 {CSU_CSLX_SEC5_5, CSU_ALL_RW},
135 {CSU_CSLX_BM, CSU_ALL_RW},
136 {CSU_CSLX_QM, CSU_ALL_RW},
137 {CSU_CSLX_GPIO2, CSU_ALL_RW},
138 {CSU_CSLX_GPIO1, CSU_ALL_RW},
139 {CSU_CSLX_GPIO4, CSU_ALL_RW},
140 {CSU_CSLX_GPIO3, CSU_ALL_RW},
141 {CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
142 {CSU_CSLX_CSU, CSU_ALL_RW},
143 {CSU_CSLX_IIC4, CSU_ALL_RW},
144 {CSU_CSLX_WDT4, CSU_ALL_RW},
145 {CSU_CSLX_WDT3, CSU_ALL_RW},
146 {CSU_CSLX_WDT5, CSU_ALL_RW},
147 {CSU_CSLX_FTM2, CSU_ALL_RW},
148 {CSU_CSLX_FTM1, CSU_ALL_RW},
149 {CSU_CSLX_FTM4, CSU_ALL_RW},
150 {CSU_CSLX_FTM3, CSU_ALL_RW},
151 {CSU_CSLX_FTM6, CSU_ALL_RW},
152 {CSU_CSLX_FTM5, CSU_ALL_RW},
153 {CSU_CSLX_FTM8, CSU_ALL_RW},
154 {CSU_CSLX_FTM7, CSU_ALL_RW},
155 {CSU_CSLX_DSCR, CSU_ALL_RW},