1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2017 NXP Semiconductor, Inc.
6 #ifndef __FSL_STREAM_ID_H
7 #define __FSL_STREAM_ID_H
10 * Stream IDs on Chassis-2 (for example ls1043a, ls1046a, ls1012) devices
11 * are not hardwired and are programmed by sw. There are a limited number
12 * of stream IDs available, and the partitioning of them is scenario
13 * dependent. This header defines the partitioning between legacy, PCI,
16 * This partitioning can be customized in this file depending
17 * on the specific hardware config:
19 * -non-PCI legacy, platform devices (USB, SDHC, SATA, DMA, QE etc)
20 * -all legacy devices get a unique stream ID assigned and programmed in
21 * their AMQR registers by u-boot
24 * -there is a range of stream IDs set aside for PCI in this
25 * file. U-boot will scan the PCI bus and for each device discovered:
26 * -allocate a streamID
27 * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID'
28 * -set a msi-map entry in the PEXn controller node in the
29 * device tree (see Documentation/devicetree/bindings/pci/pci-msi.txt
30 * for more info on the msi-map definition)
31 * -set a iommu-map entry in the PEXn controller node in the
32 * device tree (see Documentation/devicetree/bindings/pci/pci-iommu.txt
33 * for more info on the iommu-map definition)
36 * - Stream ids for DPAA1 use are reserved for future usecase.
41 #define FSL_INVALID_STREAM_ID 0
44 #define FSL_USB1_STREAM_ID 1
45 #define FSL_USB2_STREAM_ID 2
46 #define FSL_USB3_STREAM_ID 3
47 #define FSL_SDHC_STREAM_ID 4
48 #define FSL_SATA_STREAM_ID 5
49 #define FSL_QE_STREAM_ID 6
50 #define FSL_QDMA_STREAM_ID 7
51 #define FSL_EDMA_STREAM_ID 8
52 #define FSL_ETR_STREAM_ID 9
54 /* PCI - programmed in PEXn_LUT */
55 #define FSL_PEX_STREAM_ID_START 11
56 #define FSL_PEX_STREAM_ID_END 26
58 /* DPAA1 - Stream-ID that can be programmed in DPAA1 h/w */
59 #define FSL_DPAA1_STREAM_ID_START 27
60 #define FSL_DPAA1_STREAM_ID_END 63