2 * Copyright 2014, Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_
8 #define _ASM_ARMV8_FSL_LSCH3_CONFIG_
10 #include <fsl_ddrc_version.h>
12 #define CONFIG_SYS_PAGE_SIZE 0x10000
13 #define CONFIG_SYS_CACHELINE_SIZE 64
15 #ifndef L1_CACHE_BYTES
16 #define L1_CACHE_SHIFT 6
17 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
21 #define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
22 #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
23 /* Link Definitions */
24 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
26 #define CONFIG_SYS_IMMR 0x01000000
27 #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
28 #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
29 #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
30 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
31 #define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
32 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
33 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
34 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
35 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
36 #define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
37 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
38 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
39 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
40 #define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000
41 #define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
44 #define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
45 #define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
46 #define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
47 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
49 /* SP (Cortex-A5) related */
50 #define CONFIG_SYS_FSL_SP_ADDR (CONFIG_SYS_IMMR + 0x00F00000)
51 #define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR (CONFIG_SYS_FSL_SP_ADDR)
52 #define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1 (CONFIG_SYS_FSL_SP_ADDR)
53 #define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2 \
54 (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
55 #define CONFIG_SYS_FSL_SP_LOOPBACK_DUART \
56 (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
58 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
59 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
60 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
61 #define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL
63 #define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
64 #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
65 #define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
66 #define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
68 #define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
69 #define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
71 /* TZ Protection Controller Definitions */
72 #define TZPC_BASE 0x02200000
73 #define TZPCR0SIZE_BASE (TZPC_BASE)
74 #define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800)
75 #define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804)
76 #define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808)
77 #define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C)
78 #define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810)
79 #define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814)
80 #define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818)
81 #define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
82 #define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
84 /* TZ Address Space Controller Definitions */
85 #define TZASC1_BASE 0x01100000 /* as per CCSR map. */
86 #define TZASC2_BASE 0x01110000 /* as per CCSR map. */
87 #define TZASC3_BASE 0x01120000 /* as per CCSR map. */
88 #define TZASC4_BASE 0x01130000 /* as per CCSR map. */
89 #define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000)))
90 #define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004)
91 #define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008)
92 #define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100)
93 #define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104)
94 #define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108)
95 #define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C)
96 #define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110)
97 #define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114)
99 /* Generic Interrupt Controller Definitions */
100 #define GICD_BASE 0x06000000
101 #define GICR_BASE 0x06100000
103 /* SMMU Defintions */
104 #define SMMU_BASE 0x05000000 /* GR0 Base */
107 #define CONFIG_SYS_FSL_DDR_LE
108 #define CONFIG_VERY_BIG_RAM
109 #ifdef CONFIG_SYS_FSL_DDR4
110 #define CONFIG_SYS_FSL_DDRC_GEN4
112 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */
114 #define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
115 #define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
116 #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
117 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
119 #define CONFIG_SYS_FSL_ESDHC_LE
121 #define CONFIG_SYS_FSL_IFC_LE
122 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
125 #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
126 #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
127 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
128 #define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
129 #define CONFIG_SYS_PCIE1_PHYS_ADDR 0x1000000000ULL
130 #define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
131 #define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
132 #define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
134 /* Cache Coherent Interconnect */
135 #define CCI_MN_BASE 0x04000000
136 #define CCI_MN_RNF_NODEID_LIST 0x180
137 #define CCI_MN_DVM_DOMAIN_CTL 0x200
138 #define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
140 #define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
141 #define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
142 #define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
143 #define CCI_RN_I_12_BASE (CCI_MN_BASE + 0x8C0000)
144 #define CCI_RN_I_16_BASE (CCI_MN_BASE + 0x900000)
145 #define CCI_RN_I_20_BASE (CCI_MN_BASE + 0x940000)
147 #define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
148 #define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
149 #define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
151 /* Device Configuration */
152 #define DCFG_BASE 0x01e00000
153 #define DCFG_PORSR1 0x000
154 #define DCFG_PORSR1_RCW_SRC 0xff800000
155 #define DCFG_PORSR1_RCW_SRC_NOR 0x12f00000
156 #define DCFG_RCWSR13 0x130
157 #define DCFG_RCWSR13_DSPI (0 << 8)
159 #define DCFG_DCSR_BASE 0X700100000ULL
160 #define DCFG_DCSR_PORCR1 0x000
162 /* Supplemental Configuration */
163 #define SCFG_BASE 0x01fc0000
164 #define SCFG_USB3PRM1CR 0x000
166 #ifdef CONFIG_LS2085A
167 #define CONFIG_MAX_CPUS 16
168 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
169 #define CONFIG_NUM_DDR_CONTROLLERS 3
170 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
171 #define CONFIG_SYS_FSL_SRDS_1
172 #define CONFIG_SYS_FSL_SRDS_2
174 #error SoC not defined
177 #ifdef CONFIG_LS2085A
178 #define CONFIG_SYS_FSL_ERRATUM_A008336
179 #define CONFIG_SYS_FSL_ERRATUM_A008511
180 #define CONFIG_SYS_FSL_ERRATUM_A008514
181 #define CONFIG_SYS_FSL_ERRATUM_A008585
182 #define CONFIG_SYS_FSL_ERRATUM_A008751
185 #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */