1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2015 Linaro
4 * Peter Griffin <peter.griffin@linaro.org>
10 #include "hi6220_regs_alwayson.h"
12 #define HI6220_MMC0_BASE 0xF723D000
13 #define HI6220_MMC1_BASE 0xF723E000
15 #define HI6220_UART0_BASE 0xF8015000
16 #define HI6220_UART3_BASE 0xF7113000
18 #define HI6220_PMUSSI_BASE 0xF8000000
20 #define HI6220_PERI_BASE 0xF7030000
22 struct peri_sc_periph_regs {
38 u32 ddr_ctrl0; /*0x50*/
46 u32 clk0_en; /*0x200*/
52 u32 clk1_en; /*0x210*/
58 u32 clk2_en; /*0x220*/
64 u32 clk3_en; /*0x230*/
70 u32 clk8_en; /*0x240*/
76 u32 clk9_en; /*0x250*/
82 u32 clk10_en; /*0x260*/
88 u32 clk12_en; /*0x270*/
94 u32 rst0_en; /*0x300*/
100 u32 rst1_en; /*0x310*/
106 u32 rst2_en; /*0x320*/
112 u32 rst3_en; /*0x330*/
118 u32 rst8_en; /*0x340*/
124 u32 clk0_sel; /*0x400*/
128 u32 clkcfg8bit1; /*0x494*/
133 u32 reserved8_addr; /*0xd04*/
137 /* CTRL1 bit definitions */
139 #define PERI_CTRL1_ETR_AXI_CSYSREQ_N (1 << 0)
140 #define PERI_CTRL1_HIFI_INT_MASK (1 << 1)
141 #define PERI_CTRL1_HIFI_ALL_INT_MASK (1 << 2)
142 #define PERI_CTRL1_ETR_AXI_CSYSREQ_N_MSK (1 << 16)
143 #define PERI_CTRL1_HIFI_INT_MASK_MSK (1 << 17)
144 #define PERI_CTRL1_HIFI_ALL_INT_MASK_MSK (1 << 18)
147 /* CTRL2 bit definitions */
149 #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC0 (1 << 0)
150 #define PERI_CTRL2_MMC_CLK_PHASE_BYPASS_EN_MMC1 (1 << 2)
151 #define PERI_CTRL2_NAND_SYS_MEM_SEL (1 << 6)
152 #define PERI_CTRL2_G3D_DDRT_AXI_SEL (1 << 7)
153 #define PERI_CTRL2_GU_MDM_BBP_TESTPIN_SEL (1 << 8)
154 #define PERI_CTRL2_CODEC_SSI_MASTER_CHECK (1 << 9)
155 #define PERI_CTRL2_FUNC_TEST_SOFT (1 << 12)
156 #define PERI_CTRL2_CSSYS_TS_ENABLE (1 << 15)
157 #define PERI_CTRL2_HIFI_RAMCTRL_S_EMA (1 << 16)
158 #define PERI_CTRL2_HIFI_RAMCTRL_S_EMAW (1 << 20)
159 #define PERI_CTRL2_HIFI_RAMCTRL_S_EMAS (1 << 22)
160 #define PERI_CTRL2_HIFI_RAMCTRL_S_RET1N (1 << 26)
161 #define PERI_CTRL2_HIFI_RAMCTRL_S_RET2N (1 << 27)
162 #define PERI_CTRL2_HIFI_RAMCTRL_S_PGEN (1 << 28)
164 /* CTRL3 bit definitions */
166 #define PERI_CTRL3_HIFI_DDR_HARQMEM_ADDR (1 << 0)
167 #define PERI_CTRL3_HIFI_HARQMEMRMP_EN (1 << 12)
168 #define PERI_CTRL3_HARQMEM_SYS_MED_SEL (1 << 13)
169 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP1 (1 << 14)
170 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP2 (1 << 16)
171 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP3 (1 << 18)
172 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP4 (1 << 20)
173 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP5 (1 << 22)
174 #define PERI_CTRL3_SOC_AP_OCCUPY_GRP6 (1 << 24)
176 /* CTRL4 bit definitions */
178 #define PERI_CTRL4_PICO_FSELV (1 << 0)
179 #define PERI_CTRL4_FPGA_EXT_PHY_SEL (1 << 3)
180 #define PERI_CTRL4_PICO_REFCLKSEL (1 << 4)
181 #define PERI_CTRL4_PICO_SIDDQ (1 << 6)
182 #define PERI_CTRL4_PICO_SUSPENDM_SLEEPM (1 << 7)
183 #define PERI_CTRL4_PICO_OGDISABLE (1 << 8)
184 #define PERI_CTRL4_PICO_COMMONONN (1 << 9)
185 #define PERI_CTRL4_PICO_VBUSVLDEXT (1 << 10)
186 #define PERI_CTRL4_PICO_VBUSVLDEXTSEL (1 << 11)
187 #define PERI_CTRL4_PICO_VATESTENB (1 << 12)
188 #define PERI_CTRL4_PICO_SUSPENDM (1 << 14)
189 #define PERI_CTRL4_PICO_SLEEPM (1 << 15)
190 #define PERI_CTRL4_BC11_C (1 << 16)
191 #define PERI_CTRL4_BC11_B (1 << 17)
192 #define PERI_CTRL4_BC11_A (1 << 18)
193 #define PERI_CTRL4_BC11_GND (1 << 19)
194 #define PERI_CTRL4_BC11_FLOAT (1 << 20)
195 #define PERI_CTRL4_OTG_PHY_SEL (1 << 21)
196 #define PERI_CTRL4_USB_OTG_SS_SCALEDOWN_MODE (1 << 22)
197 #define PERI_CTRL4_OTG_DM_PULLDOWN (1 << 24)
198 #define PERI_CTRL4_OTG_DP_PULLDOWN (1 << 25)
199 #define PERI_CTRL4_OTG_IDPULLUP (1 << 26)
200 #define PERI_CTRL4_OTG_DRVBUS (1 << 27)
201 #define PERI_CTRL4_OTG_SESSEND (1 << 28)
202 #define PERI_CTRL4_OTG_BVALID (1 << 29)
203 #define PERI_CTRL4_OTG_AVALID (1 << 30)
204 #define PERI_CTRL4_OTG_VBUSVALID (1 << 31)
206 /* CTRL5 bit definitions */
208 #define PERI_CTRL5_USBOTG_RES_SEL (1 << 3)
209 #define PERI_CTRL5_PICOPHY_ACAENB (1 << 4)
210 #define PERI_CTRL5_PICOPHY_BC_MODE (1 << 5)
211 #define PERI_CTRL5_PICOPHY_CHRGSEL (1 << 6)
212 #define PERI_CTRL5_PICOPHY_VDATSRCEND (1 << 7)
213 #define PERI_CTRL5_PICOPHY_VDATDETENB (1 << 8)
214 #define PERI_CTRL5_PICOPHY_DCDENB (1 << 9)
215 #define PERI_CTRL5_PICOPHY_IDDIG (1 << 10)
216 #define PERI_CTRL5_DBG_MUX (1 << 11)
218 /* CTRL6 bit definitions */
220 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMA (1 << 0)
221 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAW (1 << 4)
222 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_EMAS (1 << 6)
223 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET1N (1 << 10)
224 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_RET2N (1 << 11)
225 #define PERI_CTRL6_CSSYSOFF_RAMCTRL_S_PGEN (1 << 12)
227 /* CTRL8 bit definitions */
229 #define PERI_CTRL8_PICOPHY_TXRISETUNE0 (1 << 0)
230 #define PERI_CTRL8_PICOPHY_TXPREEMPAMPTUNE0 (1 << 2)
231 #define PERI_CTRL8_PICOPHY_TXRESTUNE0 (1 << 4)
232 #define PERI_CTRL8_PICOPHY_TXHSSVTUNE0 (1 << 6)
233 #define PERI_CTRL8_PICOPHY_COMPDISTUNE0 (1 << 8)
234 #define PERI_CTRL8_PICOPHY_TXPREEMPPULSETUNE0 (1 << 11)
235 #define PERI_CTRL8_PICOPHY_OTGTUNE0 (1 << 12)
236 #define PERI_CTRL8_PICOPHY_SQRXTUNE0 (1 << 16)
237 #define PERI_CTRL8_PICOPHY_TXVREFTUNE0 (1 << 20)
238 #define PERI_CTRL8_PICOPHY_TXFSLSTUNE0 (1 << 28)
240 /* CTRL9 bit definitions */
242 #define PERI_CTRL9_PICOPLY_TESTCLKEN (1 << 0)
243 #define PERI_CTRL9_PICOPLY_TESTDATAOUTSEL (1 << 1)
244 #define PERI_CTRL9_PICOPLY_TESTADDR (1 << 4)
245 #define PERI_CTRL9_PICOPLY_TESTDATAIN (1 << 8)
247 /* CLK0 EN/DIS/STAT bit definitions */
249 #define PERI_CLK0_MMC0 (1 << 0)
250 #define PERI_CLK0_MMC1 (1 << 1)
251 #define PERI_CLK0_MMC2 (1 << 2)
252 #define PERI_CLK0_NANDC (1 << 3)
253 #define PERI_CLK0_USBOTG (1 << 4)
254 #define PERI_CLK0_PICOPHY (1 << 5)
255 #define PERI_CLK0_PLL (1 << 6)
257 /* CLK1 EN/DIS/STAT bit definitions */
259 #define PERI_CLK1_HIFI (1 << 0)
260 #define PERI_CLK1_DIGACODEC (1 << 5)
262 /* CLK2 EN/DIS/STAT bit definitions */
264 #define PERI_CLK2_IPF (1 << 0)
265 #define PERI_CLK2_SOCP (1 << 1)
266 #define PERI_CLK2_DMAC (1 << 2)
267 #define PERI_CLK2_SECENG (1 << 3)
268 #define PERI_CLK2_HPM0 (1 << 5)
269 #define PERI_CLK2_HPM1 (1 << 6)
270 #define PERI_CLK2_HPM2 (1 << 7)
271 #define PERI_CLK2_HPM3 (1 << 8)
273 /* CLK8 EN/DIS/STAT bit definitions */
275 #define PERI_CLK8_RS0 (1 << 0)
276 #define PERI_CLK8_RS2 (1 << 1)
277 #define PERI_CLK8_RS3 (1 << 2)
278 #define PERI_CLK8_MS0 (1 << 3)
279 #define PERI_CLK8_MS2 (1 << 5)
280 #define PERI_CLK8_XG2RAM0 (1 << 6)
281 #define PERI_CLK8_X2SRAM (1 << 7)
282 #define PERI_CLK8_SRAM (1 << 8)
283 #define PERI_CLK8_ROM (1 << 9)
284 #define PERI_CLK8_HARQ (1 << 10)
285 #define PERI_CLK8_MMU (1 << 11)
286 #define PERI_CLK8_DDRC (1 << 12)
287 #define PERI_CLK8_DDRPHY (1 << 13)
288 #define PERI_CLK8_DDRPHY_REF (1 << 14)
289 #define PERI_CLK8_X2X_SYSNOC (1 << 15)
290 #define PERI_CLK8_X2X_CCPU (1 << 16)
291 #define PERI_CLK8_DDRT (1 << 17)
292 #define PERI_CLK8_DDRPACK_RS (1 << 18)
294 /* CLK9 EN/DIS/STAT bit definitions */
296 #define PERI_CLK9_CARM_DAP (1 << 0)
297 #define PERI_CLK9_CARM_ATB (1 << 1)
298 #define PERI_CLK9_CARM_LBUS (1 << 2)
299 #define PERI_CLK9_CARM_KERNEL (1 << 3)
301 /* CLK10 EN/DIS/STAT bit definitions */
303 #define PERI_CLK10_IPF_CCPU (1 << 0)
304 #define PERI_CLK10_SOCP_CCPU (1 << 1)
305 #define PERI_CLK10_SECENG_CCPU (1 << 2)
306 #define PERI_CLK10_HARQ_CCPU (1 << 3)
307 #define PERI_CLK10_IPF_MCU (1 << 16)
308 #define PERI_CLK10_SOCP_MCU (1 << 17)
309 #define PERI_CLK10_SECENG_MCU (1 << 18)
310 #define PERI_CLK10_HARQ_MCU (1 << 19)
312 /* CLK12 EN/DIS/STAT bit definitions */
314 #define PERI_CLK12_HIFI_SRC (1 << 0)
315 #define PERI_CLK12_MMC0_SRC (1 << 1)
316 #define PERI_CLK12_MMC1_SRC (1 << 2)
317 #define PERI_CLK12_MMC2_SRC (1 << 3)
318 #define PERI_CLK12_SYSPLL_DIV (1 << 4)
319 #define PERI_CLK12_TPIU_SRC (1 << 5)
320 #define PERI_CLK12_MMC0_HF (1 << 6)
321 #define PERI_CLK12_MMC1_HF (1 << 7)
322 #define PERI_CLK12_PLL_TEST_SRC (1 << 8)
323 #define PERI_CLK12_CODEC_SOC (1 << 9)
324 #define PERI_CLK12_MEDIA (1 << 10)
326 /* RST0 EN/DIS/STAT bit definitions */
328 #define PERI_RST0_MMC0 (1 << 0)
329 #define PERI_RST0_MMC1 (1 << 1)
330 #define PERI_RST0_MMC2 (1 << 2)
331 #define PERI_RST0_NANDC (1 << 3)
332 #define PERI_RST0_USBOTG_BUS (1 << 4)
333 #define PERI_RST0_POR_PICOPHY (1 << 5)
334 #define PERI_RST0_USBOTG (1 << 6)
335 #define PERI_RST0_USBOTG_32K (1 << 7)
337 /* RST1 EN/DIS/STAT bit definitions */
339 #define PERI_RST1_HIFI (1 << 0)
340 #define PERI_RST1_DIGACODEC (1 << 5)
342 /* RST2 EN/DIS/STAT bit definitions */
344 #define PERI_RST2_IPF (1 << 0)
345 #define PERI_RST2_SOCP (1 << 1)
346 #define PERI_RST2_DMAC (1 << 2)
347 #define PERI_RST2_SECENG (1 << 3)
348 #define PERI_RST2_ABB (1 << 4)
349 #define PERI_RST2_HPM0 (1 << 5)
350 #define PERI_RST2_HPM1 (1 << 6)
351 #define PERI_RST2_HPM2 (1 << 7)
352 #define PERI_RST2_HPM3 (1 << 8)
354 /* RST3 EN/DIS/STAT bit definitions */
356 #define PERI_RST3_CSSYS (1 << 0)
357 #define PERI_RST3_I2C0 (1 << 1)
358 #define PERI_RST3_I2C1 (1 << 2)
359 #define PERI_RST3_I2C2 (1 << 3)
360 #define PERI_RST3_I2C3 (1 << 4)
361 #define PERI_RST3_UART1 (1 << 5)
362 #define PERI_RST3_UART2 (1 << 6)
363 #define PERI_RST3_UART3 (1 << 7)
364 #define PERI_RST3_UART4 (1 << 8)
365 #define PERI_RST3_SSP (1 << 9)
366 #define PERI_RST3_PWM (1 << 10)
367 #define PERI_RST3_BLPWM (1 << 11)
368 #define PERI_RST3_TSENSOR (1 << 12)
369 #define PERI_RST3_DAPB (1 << 18)
370 #define PERI_RST3_HKADC (1 << 19)
371 #define PERI_RST3_CODEC (1 << 20)
373 /* RST8 EN/DIS/STAT bit definitions */
375 #define PERI_RST8_RS0 (1 << 0)
376 #define PERI_RST8_RS2 (1 << 1)
377 #define PERI_RST8_RS3 (1 << 2)
378 #define PERI_RST8_MS0 (1 << 3)
379 #define PERI_RST8_MS2 (1 << 5)
380 #define PERI_RST8_XG2RAM0 (1 << 6)
381 #define PERI_RST8_X2SRAM_TZMA (1 << 7)
382 #define PERI_RST8_SRAM (1 << 8)
383 #define PERI_RST8_HARQ (1 << 10)
384 #define PERI_RST8_DDRC (1 << 12)
385 #define PERI_RST8_DDRC_APB (1 << 13)
386 #define PERI_RST8_DDRPACK_APB (1 << 14)
387 #define PERI_RST8_DDRT (1 << 17)
389 #endif /*__HI62220_H__*/