2 * (C) Copyright 2015 Linaro
3 * Peter Griffin <peter.griffin@linaro.org>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef __HI6220_ALWAYSON_H__
9 #define __HI6220_ALWAYSON_H__
11 #define ALWAYSON_CTRL_BASE 0xF7800000
13 struct alwayson_sc_regs {
27 u32 secondary_int_en0; /*0x44*/
28 u32 secondary_int_statr0;
29 u32 secondary_int_statm0;
33 u32 mcu_wkup_int_en6; /*0x54*/
34 u32 mcu_wkup_int_statr6;
35 u32 mcu_wkup_int_statm6;
39 u32 mcu_wkup_int_en5; /*0x64*/
40 u32 mcu_wkup_int_statr5;
41 u32 mcu_wkup_int_statm5;
45 u32 mcu_wkup_int_en4; /*0x94*/
46 u32 mcu_wkup_int_statr4;
47 u32 mcu_wkup_int_statm4;
51 u32 mcu_wkup_int_en0; /*0xa8*/
52 u32 mcu_wkup_int_statr0;
53 u32 mcu_wkup_int_statm0;
55 u32 mcu_wkup_int_en1; /*0xb4*/
56 u32 mcu_wkup_int_statr1;
57 u32 mcu_wkup_int_statm1;
61 u32 int_statr; /*0xc4*/
65 u32 int_en_set; /*0xd0*/
71 u32 int_statr1; /*0xc4*/
75 u32 int_en_set1; /*0xf0*/
81 u32 timer_en0; /*0x1d0*/
86 u32 timer_en4; /*0x1f0*/
91 u32 mcu_subsys_ctrl0; /*0x400*/
102 u32 mcu_subsys_stat0; /*0x440*/
103 u32 mcu_subsys_stat1;
104 u32 mcu_subsys_stat2;
105 u32 mcu_subsys_stat3;
106 u32 mcu_subsys_stat4;
107 u32 mcu_subsys_stat5;
108 u32 mcu_subsys_stat6;
109 u32 mcu_subsys_stat7;
113 u32 clk4_en; /*0x630*/
117 u32 clk5_en; /*0x63c*/
123 u32 rst4_en; /*0x6f0*/
127 u32 rst5_en; /*0x6fc*/
133 u32 pw_clk0_en; /*0x800*/
139 u32 pw_rst0_en; /*0x810*/
145 u32 pw_isoen0; /*0x820*/
151 u32 pw_mtcmos_en0; /*0x830*/
154 u32 pw_mtcmos_ack_stat0;
155 u32 pw_mtcmos_timeout_stat0;
159 u32 pw_stat0; /*0x850*/
164 u32 systest_stat; /*0x880*/
168 u32 systest_slicer_cnt0;/*0x890*/
169 u32 systest_slicer_cnt1;
173 u32 pw_ctrl1; /*0x8C8*/
182 u32 mcpu_vote_msk0; /*0x8E0*/
184 u32 mcpu_votestat0_msk;
185 u32 mcpu_votestat1_msk;
187 u32 peri_voteen; /*0x8F0*/
193 u32 peri_vote_msk0; /*0x900*/
195 u32 peri_votestat0_msk;
196 u32 erpi_votestat1_msk;
203 u32 acpu_vote_msk0; /*0x920*/
205 u32 acpu_votestat0_msk;
206 u32 acpu_votestat1_msk;
213 u32 mcu_vote_msk0; /*0x940*/
215 u32 mcu_vote_votestat0_msk;
216 u32 mcu_vote_votestat1_msk;
218 u32 unknown_18_1_2[4];
220 u32 mcu_vote_vote1en; /*0x960*/
221 u32 mcu_vote_vote1dis;
222 u32 mcu_vote_vote1stat;
226 u32 mcu_vote_vote1_msk0;/*0x970*/
227 u32 mcu_vote_vote1_msk1;
228 u32 mcu_vote_vote1stat0_msk;
229 u32 mcu_vote_vote1stat1_msk;
230 u32 mcu_vote_vote2en;
231 u32 mcu_vote_vote2dis;
232 u32 mcu_vote_vote2stat;
236 u32 mcu_vote2_msk0; /*0x990*/
238 u32 mcu_vote2stat0_msk;
239 u32 mcu_vote2stat1_msk;
241 u32 vote_stat; /*0x9a4*/
245 u32 econum; /*0xf00*/
249 u32 scchipid; /*0xf10*/
253 u32 scsocid; /*0xf1c*/
257 u32 soc_fpga_rtl_def; /*0xfe0*/
259 u32 soc_fpga_res_def0;
260 u32 soc_fpga_res_def1; /*0xfec*/
263 /* ctrl0 bit definitions */
265 #define ALWAYSON_SC_SYS_CTRL0_MODE_NORMAL 0x004
266 #define ALWAYSON_SC_SYS_CTRL0_MODE_MASK 0x007
268 /* ctrl1 bit definitions */
270 #define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG (1 << 0)
271 #define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM (1 << 1)
272 #define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP (1 << 2)
273 #define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL (1 << 3)
274 #define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG (1 << 4)
275 #define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG (1 << 6)
276 #define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG (1 << 7)
277 #define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG (1 << 8)
278 #define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG (1 << 9)
279 #define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG (1 << 10)
280 #define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1 (1 << 11)
281 #define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT (1 << 12)
282 #define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT (1 << 13)
283 #define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG (1 << 15)
284 #define ALWAYSON_SC_SYS_CTRL1_AARM_WD_RST_CFG_MSK (1 << 16)
285 #define ALWAYSON_SC_SYS_CTRL1_REMAP_SRAM_AARM_MSK (1 << 17)
286 #define ALWAYSON_SC_SYS_CTRL1_EFUSEC_REMAP_MSK (1 << 18)
287 #define ALWAYSON_SC_SYS_CTRL1_EXT_PLL_SEL_MSK (1 << 19)
288 #define ALWAYSON_SC_SYS_CTRL1_MCU_WDG0_RSTMCU_CFG_MSK (1 << 20)
289 #define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_DE_BOUNCE_CFG_MSK (1 << 22)
290 #define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_CFG_MSK (1 << 23)
291 #define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_DE_BOUNCE_CFG_MSK (1 << 24)
292 #define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_CFG_MSK (1 << 25)
293 #define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG_MSK (1 << 26)
294 #define ALWAYSON_SC_SYS_CTRL1_BUS_DFS_FORE_HD_CFG1_MSK (1 << 27)
295 #define ALWAYSON_SC_SYS_CTRL1_USIM0_HPD_OE_SFT_MSK (1 << 28)
296 #define ALWAYSON_SC_SYS_CTRL1_USIM1_HPD_OE_SFT_MSK (1 << 29)
297 #define ALWAYSON_SC_SYS_CTRL1_MCU_CLKEN_HARDCFG_MSK (1 << 31)
299 /* ctrl2 bit definitions */
301 #define ALWAYSON_SC_SYS_CTRL2_MCU_SFT_RST_STAT_CLEAR (1 << 26)
302 #define ALWAYSON_SC_SYS_CTRL2_MCU_WDG0_RST_STAT_CLEAR (1 << 27)
303 #define ALWAYSON_SC_SYS_CTRL2_TSENSOR_RST_STAT_CLEAR (1 << 28)
304 #define ALWAYSON_SC_SYS_CTRL2_ACPU_WDG_RST_STAT_CLEAR (1 << 29)
305 #define ALWAYSON_SC_SYS_CTRL2_MCU_WDG1_RST_STAT_CLEAR (1 << 30)
306 #define ALWAYSON_SC_SYS_CTRL2_GLB_SRST_STAT_CLEAR (1 << 31)
308 /* stat0 bit definitions */
310 #define ALWAYSON_SC_SYS_STAT0_MCU_RST_STAT (1 << 25)
311 #define ALWAYSON_SC_SYS_STAT0_MCU_SOFTRST_STAT (1 << 26)
312 #define ALWAYSON_SC_SYS_STAT0_MCU_WDGRST_STAT (1 << 27)
313 #define ALWAYSON_SC_SYS_STAT0_TSENSOR_HARDRST_STAT (1 << 28)
314 #define ALWAYSON_SC_SYS_STAT0_ACPU_WD_GLB_RST_STAT (1 << 29)
315 #define ALWAYSON_SC_SYS_STAT0_CM3_WDG1_RST_STAT (1 << 30)
316 #define ALWAYSON_SC_SYS_STAT0_GLB_SRST_STAT (1 << 31)
318 /* stat1 bit definitions */
320 #define ALWAYSON_SC_SYS_STAT1_MODE_STATUS (1 << 0)
321 #define ALWAYSON_SC_SYS_STAT1_BOOT_SEL_LOCK (1 << 16)
322 #define ALWAYSON_SC_SYS_STAT1_FUNC_MODE_LOCK (1 << 17)
323 #define ALWAYSON_SC_SYS_STAT1_BOOT_MODE_LOCK (1 << 19)
324 #define ALWAYSON_SC_SYS_STAT1_FUN_JTAG_MODE_OUT (1 << 20)
325 #define ALWAYSON_SC_SYS_STAT1_SECURITY_BOOT_FLG (1 << 27)
326 #define ALWAYSON_SC_SYS_STAT1_EFUSE_NANDBOOT_MSK (1 << 28)
327 #define ALWAYSON_SC_SYS_STAT1_EFUSE_NAND_BITWIDE (1 << 29)
329 /* ctrl3 bit definitions */
331 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_3 0x003
332 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_RCLK_MASK 0x007
333 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_CSSYS_CTRL_PROT (1 << 3)
334 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_TCXO_AFC_OEN_CRG (1 << 4)
335 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM1 (1 << 8)
336 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_USIM0 (1 << 9)
337 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_AOB_IO_SEL18_SD (1 << 10)
338 #define ALWAYSON_SC_MCU_SUBSYS_CTRL3_MCU_SUBSYS_CTRL3_RESERVED (1 << 11)
340 /* clk4_en bit definitions */
342 #define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_MCU (1 << 0)
343 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_MCU_DAP (1 << 3)
344 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER0 (1 << 4)
345 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_TIMER1 (1 << 5)
346 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT0 (1 << 6)
347 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_CM3_WDT1 (1 << 7)
348 #define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_S (1 << 8)
349 #define ALWAYSON_SC_PERIPH_CLK4_EN_HCLK_IPC_NS (1 << 9)
350 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_EFUSEC (1 << 10)
351 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TZPC (1 << 11)
352 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT0 (1 << 12)
353 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT1 (1 << 13)
354 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_WDT2 (1 << 14)
355 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER0 (1 << 15)
356 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER1 (1 << 16)
357 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER2 (1 << 17)
358 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER3 (1 << 18)
359 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER4 (1 << 19)
360 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER5 (1 << 20)
361 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER6 (1 << 21)
362 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER7 (1 << 22)
363 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_TIMER8 (1 << 23)
364 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_UART0 (1 << 24)
365 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC0 (1 << 25)
366 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_RTC1 (1 << 26)
367 #define ALWAYSON_SC_PERIPH_CLK4_EN_PCLK_PMUSSI (1 << 27)
368 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_JTAG_AUTH (1 << 28)
369 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_CS_DAPB_ON (1 << 29)
370 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_PDM (1 << 30)
371 #define ALWAYSON_SC_PERIPH_CLK4_EN_CLK_SSI_PAD (1 << 31)
373 /* clk5_en bit definitions */
375 #define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_CCPU (1 << 0)
376 #define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_CCPU (1 << 1)
377 #define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_CCPU (1 << 2)
378 #define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_CCPU (1 << 3)
379 #define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_PMUSSI_MCU (1 << 16)
380 #define ALWAYSON_SC_PERIPH_CLK5_EN_PCLK_EFUSEC_MCU (1 << 17)
381 #define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_MCU (1 << 18)
382 #define ALWAYSON_SC_PERIPH_CLK5_EN_HCLK_IPC_NS_MCU (1 << 19)
384 /* rst4_dis bit definitions */
386 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_ECTR_N (1 << 0)
387 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_SYS_N (1 << 1)
388 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_POR_N (1 << 2)
389 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_MCU_DAP_N (1 << 3)
390 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER0_N (1 << 4)
391 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_TIMER1_N (1 << 5)
392 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT0_N (1 << 6)
393 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_CM3_WDT1_N (1 << 7)
394 #define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_S_N (1 << 8)
395 #define ALWAYSON_SC_PERIPH_RST4_DIS_HRESET_IPC_NS_N (1 << 9)
396 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_EFUSEC_N (1 << 10)
397 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT0_N (1 << 12)
398 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT1_N (1 << 13)
399 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_WDT2_N (1 << 14)
400 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER0_N (1 << 15)
401 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER1_N (1 << 16)
402 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER2_N (1 << 17)
403 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER3_N (1 << 18)
404 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER4_N (1 << 19)
405 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER5_N (1 << 20)
406 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER6_N (1 << 21)
407 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER7_N (1 << 22)
408 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_TIMER8_N (1 << 23)
409 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_UART0_N (1 << 24)
410 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC0_N (1 << 25)
411 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_RTC1_N (1 << 26)
412 #define ALWAYSON_SC_PERIPH_RST4_DIS_PRESET_PMUSSI_N (1 << 27)
413 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_JTAG_AUTH_N (1 << 28)
414 #define ALWAYSON_SC_PERIPH_RST4_DIS_RESET_CS_DAPB_ON_N (1 << 29)
415 #define ALWAYSON_SC_PERIPH_RST4_DIS_MDM_SUBSYS_GLB (1 << 30)
417 #define PCLK_TIMER1 (1 << 16)
418 #define PCLK_TIMER0 (1 << 15)
420 #endif /* __HI6220_ALWAYSON_H__ */