2 * K2HK: Clock management APIs
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef __ASM_ARCH_CLOCK_K2HK_H
11 #define __ASM_ARCH_CLOCK_K2HK_H
13 #include <asm/arch/hardware.h>
30 ext_clk_count /* number of external clocks */
33 extern unsigned int external_clk[ext_clk_count];
59 #define K2HK_CLK1_6 sys_clk0_6_clk
69 #define MAIN_PLL CORE_PLL
71 /* PLL configuration data */
72 struct pll_init_data {
74 int pll_m; /* PLL Multiplier */
75 int pll_d; /* PLL divider */
76 int pll_od; /* PLL output divider */
79 #define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
80 #define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
81 #define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
82 #define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
83 #define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
84 #define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
85 #define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
86 #define TETRIS_PLL_500 {TETRIS_PLL, 8, 1, 2}
87 #define TETRIS_PLL_750 {TETRIS_PLL, 12, 1, 2}
88 #define TETRIS_PLL_687 {TETRIS_PLL, 11, 1, 2}
89 #define TETRIS_PLL_625 {TETRIS_PLL, 10, 1, 2}
90 #define TETRIS_PLL_812 {TETRIS_PLL, 13, 1, 2}
91 #define TETRIS_PLL_875 {TETRIS_PLL, 14, 1, 2}
92 #define TETRIS_PLL_1188 {TETRIS_PLL, 19, 2, 1}
93 #define TETRIS_PLL_1200 {TETRIS_PLL, 48, 5, 1}
94 #define TETRIS_PLL_1375 {TETRIS_PLL, 22, 2, 1}
95 #define TETRIS_PLL_1400 {TETRIS_PLL, 56, 5, 1}
96 #define DDR3_PLL_200(x) {DDR3##x##_PLL, 4, 1, 2}
97 #define DDR3_PLL_400(x) {DDR3##x##_PLL, 16, 1, 4}
98 #define DDR3_PLL_800(x) {DDR3##x##_PLL, 16, 1, 2}
99 #define DDR3_PLL_333(x) {DDR3##x##_PLL, 20, 1, 6}
101 void init_plls(int num_pll, struct pll_init_data *config);
102 void init_pll(const struct pll_init_data *data);
103 unsigned long clk_get_rate(unsigned int clk);
104 unsigned long clk_round_rate(unsigned int clk, unsigned long hz);
105 int clk_set_rate(unsigned int clk, unsigned long hz);