git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-keystone/hardware-k2hk.h

   1 /*
   2  * K2HK: SoC definitions
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
  11 #define __ASM_ARCH_HARDWARE_K2HK_H
  12
  13 #define KS2_PLL_CNTRL_BASE              0x02310000
  14 #define KS2_CLOCK_BASE                  KS2_PLL_CNTRL_BASE
  15 #define KS2_RSTCTRL                     (KS2_PLL_CNTRL_BASE + 0xe8)
  16 #define KS2_RSTCTRL_KEY                 0x5a69
  17 #define KS2_RSTCTRL_MASK                0xffff0000
  18 #define KS2_RSTCTRL_SWRST               0xfffe0000
  19
  20 #define KS2_DEVICE_STATE_CTRL_BASE      0x02620000
  21 #define KS2_JTAG_ID_REG                 (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
  22 #define KS2_DEVSTAT                     (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
  23
  24 #define KS2_MISC_CTRL                   (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
  25
  26 #define KS2_ARM_PLL_EN                  BIT(13)
  27
  28 #define KS2_SPI0_BASE                   0x21000400
  29 #define KS2_SPI1_BASE                   0x21000600
  30 #define KS2_SPI2_BASE                   0x21000800
  31 #define KS2_SPI_BASE                    KS2_SPI0_BASE
  32
  33 /* Chip configuration unlock codes and registers */
  34 #define KS2_KICK0                       (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
  35 #define KS2_KICK1                       (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
  36 #define KS2_KICK0_MAGIC                 0x83e70b13
  37 #define KS2_KICK1_MAGIC                 0x95a4f1e0
  38
  39 /* PA SS Registers */
  40 #define KS2_PASS_BASE                   0x02000000
  41
  42 /* PLL control registers */
  43 #define KS2_MAINPLLCTL0                 (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
  44 #define KS2_MAINPLLCTL1                 (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
  45 #define KS2_PASSPLLCTL0                 (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
  46 #define KS2_PASSPLLCTL1                 (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
  47 #define KS2_DDR3APLLCTL0                (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
  48 #define KS2_DDR3APLLCTL1                (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
  49 #define KS2_DDR3BPLLCTL0                (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
  50 #define KS2_DDR3BPLLCTL1                (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
  51 #define KS2_ARMPLLCTL0                  (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
  52 #define KS2_ARMPLLCTL1                  (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
  53
  54 /* Power and Sleep Controller (PSC) Domains */
  55 #define KS2_LPSC_MOD                    0
  56 #define KS2_LPSC_DUMMY1                 1
  57 #define KS2_LPSC_USB                    2
  58 #define KS2_LPSC_EMIF25_SPI             3
  59 #define KS2_LPSC_TSIP                   4
  60 #define KS2_LPSC_DEBUGSS_TRC            5
  61 #define KS2_LPSC_TETB_TRC               6
  62 #define KS2_LPSC_PKTPROC                7
  63 #define KS2_LPSC_PA                     KS2_LPSC_PKTPROC
  64 #define KS2_LPSC_SGMII                  8
  65 #define KS2_LPSC_CPGMAC                 KS2_LPSC_SGMII
  66 #define KS2_LPSC_CRYPTO                 9
  67 #define KS2_LPSC_PCIE                   10
  68 #define KS2_LPSC_SRIO                   11
  69 #define KS2_LPSC_VUSR0                  12
  70 #define KS2_LPSC_CHIP_SRSS              13
  71 #define KS2_LPSC_MSMC                   14
  72 #define KS2_LPSC_GEM_1                  16
  73 #define KS2_LPSC_GEM_2                  17
  74 #define KS2_LPSC_GEM_3                  18
  75 #define KS2_LPSC_GEM_4                  19
  76 #define KS2_LPSC_GEM_5                  20
  77 #define KS2_LPSC_GEM_6                  21
  78 #define KS2_LPSC_GEM_7                  22
  79 #define KS2_LPSC_EMIF4F_DDR3A           23
  80 #define KS2_LPSC_EMIF4F_DDR3B           24
  81 #define KS2_LPSC_TAC                    25
  82 #define KS2_LPSC_RAC                    26
  83 #define KS2_LPSC_RAC_1                  27
  84 #define KS2_LPSC_FFTC_A                 28
  85 #define KS2_LPSC_FFTC_B                 29
  86 #define KS2_LPSC_FFTC_C                 30
  87 #define KS2_LPSC_FFTC_D                 31
  88 #define KS2_LPSC_FFTC_E                 32
  89 #define KS2_LPSC_FFTC_F                 33
  90 #define KS2_LPSC_AI2                    34
  91 #define KS2_LPSC_TCP3D_0                35
  92 #define KS2_LPSC_TCP3D_1                36
  93 #define KS2_LPSC_TCP3D_2                37
  94 #define KS2_LPSC_TCP3D_3                38
  95 #define KS2_LPSC_VCP2X4_A               39
  96 #define KS2_LPSC_CP2X4_B                40
  97 #define KS2_LPSC_VCP2X4_C               41
  98 #define KS2_LPSC_VCP2X4_D               42
  99 #define KS2_LPSC_VCP2X4_E               43
 100 #define KS2_LPSC_VCP2X4_F               44
 101 #define KS2_LPSC_VCP2X4_G               45
 102 #define KS2_LPSC_VCP2X4_H               46
 103 #define KS2_LPSC_BCP                    47
 104 #define KS2_LPSC_DXB                    48
 105 #define KS2_LPSC_VUSR1                  49
 106 #define KS2_LPSC_XGE                    50
 107 #define KS2_LPSC_ARM_SREFLEX            51
 108
 109 /* DDR3A definitions */
 110 #define KS2_DDR3A_EMIF_CTRL_BASE        0x21010000
 111 #define KS2_DDR3A_EMIF_DATA_BASE        0x80000000
 112 #define KS2_DDR3A_DDRPHYC               0x02329000
 113 /* DDR3B definitions */
 114 #define KS2_DDR3B_EMIF_CTRL_BASE        0x21020000
 115 #define KS2_DDR3B_EMIF_DATA_BASE        0x60000000
 116 #define KS2_DDR3B_DDRPHYC               0x02328000
 117
 118 /* Queue manager */
 119 #define KS2_QM_MANAGER_BASE             0x02a02000
 120 #define KS2_QM_DESC_SETUP_BASE          0x02a03000
 121 #define KS2_QM_MANAGER_QUEUES_BASEi     0x02a80000
 122 #define KS2_QM_MANAGER_Q_PROXY_BASE     0x02ac0000
 123 #define KS2_QM_QUEUE_STATUS_BASE        0x02a40000
 124
 125 /* MSMC control */
 126 #define KS2_MSMC_CTRL_BASE              0x0bc00000
 127
 128 /* Number of DSP cores */
 129 #define KS2_NUM_DSPS                    8
 130
 131 #endif /* __ASM_ARCH_HARDWARE_H */