git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-keystone/hardware-k2hk.h

   1 /*
   2  * K2HK: SoC definitions
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
  10 #define __ASM_ARCH_HARDWARE_K2HK_H
  11
  12 #define K2HK_PLL_CNTRL_BASE             0x02310000
  13 #define CLOCK_BASE                      K2HK_PLL_CNTRL_BASE
  14 #define KS2_RSTCTRL                     (K2HK_PLL_CNTRL_BASE + 0xe8)
  15 #define KS2_RSTCTRL_KEY                 0x5a69
  16 #define KS2_RSTCTRL_MASK                0xffff0000
  17 #define KS2_RSTCTRL_SWRST               0xfffe0000
  18
  19 #define KS2_DEVICE_STATE_CTRL_BASE      0x02620000
  20 #define JTAG_ID_REG                     (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
  21 #define K2HK_DEVSTAT                    (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
  22
  23 #define K2HK_MISC_CTRL                  (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
  24
  25 #define ARM_PLL_EN                      BIT(13)
  26
  27 #define K2HK_SPI0_BASE                  0x21000400
  28 #define K2HK_SPI1_BASE                  0x21000600
  29 #define K2HK_SPI2_BASE                  0x21000800
  30 #define K2HK_SPI_BASE                   K2HK_SPI0_BASE
  31
  32 /* Chip configuration unlock codes and registers */
  33 #define KEYSTONE_KICK0                 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
  34 #define KEYSTONE_KICK1                 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
  35 #define KEYSTONE_KICK0_MAGIC           0x83e70b13
  36 #define KEYSTONE_KICK1_MAGIC           0x95a4f1e0
  37
  38 /* PA SS Registers */
  39 #define KS2_PASS_BASE                  0x02000000
  40
  41 /* PLL control registers */
  42 #define K2HK_MAINPLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
  43 #define K2HK_MAINPLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
  44 #define K2HK_PASSPLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
  45 #define K2HK_PASSPLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
  46 #define K2HK_DDR3APLLCTL0              (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
  47 #define K2HK_DDR3APLLCTL1              (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
  48 #define K2HK_DDR3BPLLCTL0              (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
  49 #define K2HK_DDR3BPLLCTL1              (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
  50 #define K2HK_ARMPLLCTL0                (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
  51 #define K2HK_ARMPLLCTL1                (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
  52
  53 /* Power and Sleep Controller (PSC) Domains */
  54 #define K2HK_LPSC_MOD                  0
  55 #define K2HK_LPSC_DUMMY1               1
  56 #define K2HK_LPSC_USB                  2
  57 #define K2HK_LPSC_EMIF25_SPI           3
  58 #define K2HK_LPSC_TSIP                 4
  59 #define K2HK_LPSC_DEBUGSS_TRC          5
  60 #define K2HK_LPSC_TETB_TRC             6
  61 #define K2HK_LPSC_PKTPROC              7
  62 #define KS2_LPSC_PA                    K2HK_LPSC_PKTPROC
  63 #define K2HK_LPSC_SGMII                8
  64 #define KS2_LPSC_CPGMAC                K2HK_LPSC_SGMII
  65 #define K2HK_LPSC_CRYPTO               9
  66 #define K2HK_LPSC_PCIE                 10
  67 #define K2HK_LPSC_SRIO                 11
  68 #define K2HK_LPSC_VUSR0                12
  69 #define K2HK_LPSC_CHIP_SRSS            13
  70 #define K2HK_LPSC_MSMC                 14
  71 #define K2HK_LPSC_GEM_1                16
  72 #define K2HK_LPSC_GEM_2                17
  73 #define K2HK_LPSC_GEM_3                18
  74 #define K2HK_LPSC_GEM_4                19
  75 #define K2HK_LPSC_GEM_5                20
  76 #define K2HK_LPSC_GEM_6                21
  77 #define K2HK_LPSC_GEM_7                22
  78 #define K2HK_LPSC_EMIF4F_DDR3A         23
  79 #define K2HK_LPSC_EMIF4F_DDR3B         24
  80 #define K2HK_LPSC_TAC                  25
  81 #define K2HK_LPSC_RAC                  26
  82 #define K2HK_LPSC_RAC_1                27
  83 #define K2HK_LPSC_FFTC_A               28
  84 #define K2HK_LPSC_FFTC_B               29
  85 #define K2HK_LPSC_FFTC_C               30
  86 #define K2HK_LPSC_FFTC_D               31
  87 #define K2HK_LPSC_FFTC_E               32
  88 #define K2HK_LPSC_FFTC_F               33
  89 #define K2HK_LPSC_AI2                  34
  90 #define K2HK_LPSC_TCP3D_0              35
  91 #define K2HK_LPSC_TCP3D_1              36
  92 #define K2HK_LPSC_TCP3D_2              37
  93 #define K2HK_LPSC_TCP3D_3              38
  94 #define K2HK_LPSC_VCP2X4_A             39
  95 #define K2HK_LPSC_CP2X4_B              40
  96 #define K2HK_LPSC_VCP2X4_C             41
  97 #define K2HK_LPSC_VCP2X4_D             42
  98 #define K2HK_LPSC_VCP2X4_E             43
  99 #define K2HK_LPSC_VCP2X4_F             44
 100 #define K2HK_LPSC_VCP2X4_G             45
 101 #define K2HK_LPSC_VCP2X4_H             46
 102 #define K2HK_LPSC_BCP                  47
 103 #define K2HK_LPSC_DXB                  48
 104 #define K2HK_LPSC_VUSR1                49
 105 #define K2HK_LPSC_XGE                  50
 106 #define K2HK_LPSC_ARM_SREFLEX          51
 107
 108 /* DDR3A definitions */
 109 #define K2HK_DDR3A_EMIF_CTRL_BASE      0x21010000
 110 #define K2HK_DDR3A_EMIF_DATA_BASE      0x80000000
 111 #define K2HK_DDR3A_DDRPHYC             0x02329000
 112 /* DDR3B definitions */
 113 #define K2HK_DDR3B_EMIF_CTRL_BASE      0x21020000
 114 #define K2HK_DDR3B_EMIF_DATA_BASE      0x60000000
 115 #define K2HK_DDR3B_DDRPHYC             0x02328000
 116
 117 /* Queue manager */
 118 #define DEVICE_QM_MANAGER_BASE         0x02a02000
 119 #define DEVICE_QM_DESC_SETUP_BASE      0x02a03000
 120 #define DEVICE_QM_MANAGER_QUEUES_BASE  0x02a80000
 121 #define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
 122 #define DEVICE_QM_QUEUE_STATUS_BASE    0x02a40000
 123 #define DEVICE_QM_NUM_LINKRAMS         2
 124 #define DEVICE_QM_NUM_MEMREGIONS       20
 125
 126 #define DEVICE_PA_CDMA_GLOBAL_CFG_BASE  0x02004000
 127 #define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
 128 #define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
 129 #define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
 130
 131 #define DEVICE_PA_CDMA_RX_NUM_CHANNELS  24
 132 #define DEVICE_PA_CDMA_RX_NUM_FLOWS     32
 133 #define DEVICE_PA_CDMA_TX_NUM_CHANNELS  9
 134
 135 /* MSMC control */
 136 #define K2HK_MSMC_CTRL_BASE             0x0bc00000
 137
 138 /* Number of DSP cores */
 139 #define KS2_NUM_DSPS                    8
 140
 141 #endif /* __ASM_ARCH_HARDWARE_H */