2 * Keystone2: Common SoC definitions, structures etc.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef __ASM_ARCH_HARDWARE_H
10 #define __ASM_ARCH_HARDWARE_H
16 #include <linux/sizes.h>
19 #define REG(addr) (*(volatile unsigned int *)(addr))
20 #define REG_P(addr) ((volatile unsigned int *)(addr))
22 typedef volatile unsigned int dv_reg;
23 typedef volatile unsigned int *dv_reg_p;
25 struct ddr3_phy_config {
27 unsigned int pgcr1_mask;
28 unsigned int pgcr1_val;
34 unsigned int dcr_mask;
51 struct ddr3_emif_config {
63 #define BIT(x) (1 << (x))
65 #define KS2_DDRPHY_PIR_OFFSET 0x04
66 #define KS2_DDRPHY_PGCR0_OFFSET 0x08
67 #define KS2_DDRPHY_PGCR1_OFFSET 0x0C
68 #define KS2_DDRPHY_PGSR0_OFFSET 0x10
69 #define KS2_DDRPHY_PGSR1_OFFSET 0x14
70 #define KS2_DDRPHY_PLLCR_OFFSET 0x18
71 #define KS2_DDRPHY_PTR0_OFFSET 0x1C
72 #define KS2_DDRPHY_PTR1_OFFSET 0x20
73 #define KS2_DDRPHY_PTR2_OFFSET 0x24
74 #define KS2_DDRPHY_PTR3_OFFSET 0x28
75 #define KS2_DDRPHY_PTR4_OFFSET 0x2C
76 #define KS2_DDRPHY_DCR_OFFSET 0x44
78 #define KS2_DDRPHY_DTPR0_OFFSET 0x48
79 #define KS2_DDRPHY_DTPR1_OFFSET 0x4C
80 #define KS2_DDRPHY_DTPR2_OFFSET 0x50
82 #define KS2_DDRPHY_MR0_OFFSET 0x54
83 #define KS2_DDRPHY_MR1_OFFSET 0x58
84 #define KS2_DDRPHY_MR2_OFFSET 0x5C
85 #define KS2_DDRPHY_DTCR_OFFSET 0x68
86 #define KS2_DDRPHY_PGCR2_OFFSET 0x8C
88 #define KS2_DDRPHY_ZQ0CR1_OFFSET 0x184
89 #define KS2_DDRPHY_ZQ1CR1_OFFSET 0x194
90 #define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
91 #define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
93 #define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
95 #define IODDRM_MASK 0x00000180
96 #define ZCKSEL_MASK 0x01800000
97 #define CL_MASK 0x00000072
98 #define WR_MASK 0x00000E00
99 #define BL_MASK 0x00000003
100 #define RRMODE_MASK 0x00040000
101 #define UDIMM_MASK 0x20000000
102 #define BYTEMASK_MASK 0x0003FC00
103 #define MPRDQ_MASK 0x00000080
104 #define PDQ_MASK 0x00000070
105 #define NOSRA_MASK 0x08000000
106 #define ECC_MASK 0x00000001
108 #define KS2_DDR3_MIDR_OFFSET 0x00
109 #define KS2_DDR3_STATUS_OFFSET 0x04
110 #define KS2_DDR3_SDCFG_OFFSET 0x08
111 #define KS2_DDR3_SDRFC_OFFSET 0x10
112 #define KS2_DDR3_SDTIM1_OFFSET 0x18
113 #define KS2_DDR3_SDTIM2_OFFSET 0x1C
114 #define KS2_DDR3_SDTIM3_OFFSET 0x20
115 #define KS2_DDR3_SDTIM4_OFFSET 0x28
116 #define KS2_DDR3_PMCTL_OFFSET 0x38
117 #define KS2_DDR3_ZQCFG_OFFSET 0xC8
119 #define KS2_UART0_BASE 0x02530c00
120 #define KS2_UART1_BASE 0x02531000
123 #define KS2_AEMIF_CNTRL_BASE 0x21000a00
124 #define DAVINCI_ASYNC_EMIF_CNTRL_BASE KS2_AEMIF_CNTRL_BASE
126 #ifdef CONFIG_SOC_K2HK
127 #include <asm/arch/hardware-k2hk.h>
131 static inline int cpu_is_k2hk(void)
133 unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
134 unsigned int part_no = (jtag_id >> 12) & 0xffff;
136 return (part_no == 0xb981) ? 1 : 0;
139 static inline int cpu_revision(void)
141 unsigned int jtag_id = __raw_readl(JTAG_ID_REG);
142 unsigned int rev = (jtag_id >> 28) & 0xf;
147 void share_all_segments(int priv_id);
148 int cpu_to_bus(u32 *ptr, u32 length);
149 void init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
150 void init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
151 void init_ddr3(void);
152 void sdelay(unsigned long);
156 #endif /* __ASM_ARCH_HARDWARE_H */