2 * Multicore Navigator definitions
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
7 * SPDX-License-Identifier: GPL-2.0+
10 #ifndef _KEYSTONE_NAV_H_
11 #define _KEYSTONE_NAV_H_
13 #include <asm/arch/hardware.h>
22 #define QM_DESC_TYPE_HOST 0
23 #define QM_DESC_PSINFO_IN_DESCR 0
24 #define QM_DESC_DEFAULT_DESCINFO (QM_DESC_TYPE_HOST << 30) | \
25 (QM_DESC_PSINFO_IN_DESCR << 22)
28 #define QM_DESC_PINFO_EPIB 1
29 #define QM_DESC_PINFO_RETURN_OWN 1
30 #define QM_DESC_DEFAULT_PINFO (QM_DESC_PINFO_EPIB << 31) | \
31 (QM_DESC_PINFO_RETURN_OWN << 15)
45 struct descr_mem_setup_reg {
60 /* QM module addresses */
61 u32 stat_cfg; /* status and config */
62 struct qm_reg_queue *queue; /* management region */
63 u32 mngr_vbusm; /* management region (VBUSM) */
64 u32 i_lram; /* internal linking RAM */
65 struct qm_reg_queue *proxy;
67 struct qm_cfg_reg *mngr_cfg;
68 /* Queue manager config region */
69 u32 intd_cfg; /* QMSS INTD config region */
70 struct descr_mem_setup_reg *desc_mem;
71 /* descritor memory setup region*/
73 u32 pdsp_cmd; /* PDSP1 command interface */
74 u32 pdsp_ctl; /* PDSP1 control registers */
76 /* QM configuration parameters */
99 void qm_push(struct qm_host_desc *hd, u32 qnum);
100 struct qm_host_desc *qm_pop(u32 qnum);
102 void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
103 void *buff_ptr, u32 buff_len);
105 struct qm_host_desc *qm_pop_from_free_pool(void);
106 void queue_close(u32 qnum);
111 #define CPDMA_REG_VAL_MAKE_RX_FLOW_A(einfo, psinfo, rxerr, desc, \
112 psloc, sopoff, qmgr, qnum) \
113 (((einfo & 1) << 30) | \
114 ((psinfo & 1) << 29) | \
115 ((rxerr & 1) << 28) | \
116 ((desc & 3) << 26) | \
117 ((psloc & 1) << 25) | \
118 ((sopoff & 0x1ff) << 16) | \
119 ((qmgr & 3) << 12) | \
120 ((qnum & 0xfff) << 0))
122 #define CPDMA_REG_VAL_MAKE_RX_FLOW_D(fd0qm, fd0qnum, fd1qm, fd1qnum) \
123 (((fd0qm & 3) << 28) | \
124 ((fd0qnum & 0xfff) << 16) | \
125 ((fd1qm & 3) << 12) | \
126 ((fd1qnum & 0xfff) << 0))
128 #define CPDMA_CHAN_A_ENABLE ((u32)1 << 31)
129 #define CPDMA_CHAN_A_TDOWN (1 << 30)
130 #define TDOWN_TIMEOUT_COUNT 100
132 struct global_ctl_regs {
135 u32 emulation_control;
136 u32 priority_control;
140 struct tx_chan_regs {
146 struct rx_chan_regs {
151 struct rx_flow_regs {
160 struct global_ctl_regs *global;
161 struct tx_chan_regs *tx_ch;
163 struct rx_chan_regs *rx_ch;
166 struct rx_flow_regs *rx_flows;
173 u32 rx_flow; /* flow that is used for RX */
177 * packet dma user allocates memory for rx buffers
178 * and describe it in the following structure
180 struct rx_buff_desc {
187 int netcp_close(void);
188 int netcp_init(struct rx_buff_desc *rx_buffers);
189 int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2);
190 void *netcp_recv(u32 **pkt, int *num_bytes);
191 void netcp_release_rxhd(void *hd);
193 #endif /* _KEYSTONE_NAV_H_ */