3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Lei Wen <leiwen@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
10 * This file should be included in board config header file.
12 * It supports common definitions for Kirkwood platform
18 #if defined (CONFIG_KW88F6281)
19 #include <asm/arch/kw88f6281.h>
20 #elif defined (CONFIG_KW88F6192)
21 #include <asm/arch/kw88f6192.h>
23 #error "SOC Name not defined"
24 #endif /* CONFIG_KW88F6281 */
26 #include <asm/arch/kirkwood.h>
27 #define CONFIG_ARM926EJS 1 /* Basic Architecture */
28 #define CONFIG_SYS_CACHELINE_SIZE 32
29 /* default Dcache Line length for kirkwood */
30 #define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
31 #define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
32 #define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
33 #define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
36 * By default kwbimage.cfg from board specific folder is used
37 * If for some board, different configuration file need to be used,
38 * CONFIG_SYS_KWD_CONFIG should be defined in board specific header file
40 #ifndef CONFIG_SYS_KWD_CONFIG
41 #define CONFIG_SYS_KWD_CONFIG $(SRCTREE)/$(CONFIG_BOARDDIR)/kwbimage.cfg
42 #endif /* CONFIG_SYS_KWD_CONFIG */
44 /* Kirkwood has 2k of Security SRAM, use it for SP */
45 #define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
46 #define CONFIG_NR_DRAM_BANKS_MAX 2
48 #define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
49 #define MV_UART_CONSOLE_BASE KW_UART0_BASE
50 #define MV_SATA_BASE KW_SATA_BASE
51 #define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
52 #define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
57 #ifdef CONFIG_CMD_NAND
58 #define CONFIG_NAND_KIRKWOOD
59 #define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
60 #define NAND_ALLOW_ERASE_ALL 1
64 * SPI Flash configuration
67 #define CONFIG_HARD_SPI 1
68 #define CONFIG_KIRKWOOD_SPI 1
69 #ifndef CONFIG_ENV_SPI_BUS
70 # define CONFIG_ENV_SPI_BUS 0
72 #ifndef CONFIG_ENV_SPI_CS
73 # define CONFIG_ENV_SPI_CS 0
75 #ifndef CONFIG_ENV_SPI_MAX_HZ
76 # define CONFIG_ENV_SPI_MAX_HZ 50000000
81 * Ethernet Driver configuration
84 #define CONFIG_CMD_MII
85 #define CONFIG_NETCONSOLE /* include NetConsole support */
86 #define CONFIG_MII /* expose smi ove miiphy interface */
87 #define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
88 #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
89 #define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
90 #define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
91 #endif /* CONFIG_CMD_NET */
97 #define CONFIG_USB_EHCI_MARVELL
98 #define CONFIG_EHCI_IS_TDI
99 #endif /* CONFIG_CMD_USB */
102 * IDE Support on SATA ports
104 #ifdef CONFIG_CMD_IDE
106 #define CONFIG_CMD_EXT2
107 #define CONFIG_MVSATA_IDE
108 #define CONFIG_IDE_PREINIT
109 #define CONFIG_MVSATA_IDE_USE_PORT1
110 /* Needs byte-swapping for ATA data register */
111 #define CONFIG_IDE_SWAP_IO
112 /* Data, registers and alternate blocks are at the same offset */
113 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
114 #define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
115 #define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
116 /* Each 8-bit ATA register is aligned to a 4-bytes address */
117 #define CONFIG_SYS_ATA_STRIDE 4
118 /* Controller supports 48-bits LBA addressing */
120 /* CONFIG_CMD_IDE requires some #defines for ATA registers */
121 #define CONFIG_SYS_IDE_MAXBUS 2
122 #define CONFIG_SYS_IDE_MAXDEVICE 2
123 /* ATA registers base is at SATA controller base */
124 #define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
125 #endif /* CONFIG_CMD_IDE */
130 #ifdef CONFIG_CMD_I2C
131 #ifndef CONFIG_SYS_I2C_SOFT
132 #define CONFIG_I2C_MVTWSI
134 #define CONFIG_SYS_I2C_SLAVE 0x0
135 #define CONFIG_SYS_I2C_SPEED 100000
138 #endif /* _KW_CONFIG_H */