3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28 #include <asm/system.h>
32 #define KWCPU_WIN_CTRL_DATA(size, target, attr, en) (en | (target << 4) \
33 | (attr << 8) | (kw_winctrl_calcsize(size) << 16))
35 #define KWGBE_PORT_SERIAL_CONTROL1_REG(_x) \
36 ((_x ? KW_EGIGA0_BASE : KW_EGIGA1_BASE) + 0x44c)
38 #define KW_REG_PCIE_DEVID (KW_REG_PCIE_BASE + 0x00)
39 #define KW_REG_PCIE_REVID (KW_REG_PCIE_BASE + 0x08)
40 #define KW_REG_DEVICE_ID (KW_MPP_BASE + 0x34)
41 #define KW_REG_SYSRST_CNT (KW_MPP_BASE + 0x50)
42 #define SYSRST_CNT_1SEC_VAL (25*1000000)
43 #define KW_REG_MPP_OUT_DRV_REG (KW_MPP_BASE + 0xE0)
58 KWCPU_TARGET_RESERVED,
60 KWCPU_TARGET_1RESERVED,
66 KWCPU_ATTR_SASRAM = 0x01,
67 KWCPU_ATTR_DRAM_CS0 = 0x0e,
68 KWCPU_ATTR_DRAM_CS1 = 0x0d,
69 KWCPU_ATTR_DRAM_CS2 = 0x0b,
70 KWCPU_ATTR_DRAM_CS3 = 0x07,
71 KWCPU_ATTR_NANDFLASH = 0x2f,
72 KWCPU_ATTR_SPIFLASH = 0x1e,
73 KWCPU_ATTR_BOOTROM = 0x1d,
74 KWCPU_ATTR_PCIE_IO = 0xe0,
75 KWCPU_ATTR_PCIE_MEM = 0xe8
79 * Default Device Address MAP BAR values
81 #define KW_DEFADR_PCI_MEM 0x90000000
82 #define KW_DEFADR_PCI_IO 0xC0000000
83 #define KW_DEFADR_PCI_IO_REMAP 0xC0000000
84 #define KW_DEFADR_SASRAM 0xC8010000
85 #define KW_DEFADR_NANDF 0xD8000000
86 #define KW_DEFADR_SPIF 0xE8000000
87 #define KW_DEFADR_BOOTROM 0xF8000000
90 * read feroceon/sheeva core extra feature register
91 * using co-proc instruction
93 static inline unsigned int readfr_extra_feature_reg(void)
96 asm volatile ("mrc p15, 1, %0, c15, c1, 0 @ readfr exfr":"=r"
102 * write feroceon/sheeva core extra feature register
103 * using co-proc instruction
105 static inline void writefr_extra_feature_reg(unsigned int val)
107 asm volatile ("mcr p15, 1, %0, c15, c1, 0 @ writefr exfr"::"r"
113 * MBus-L to Mbus Bridge Registers
114 * Ref: Datasheet sec:A.3
116 struct kwwin_registers {
124 * CPU control and status Registers
125 * Ref: Datasheet sec:A.3.2
127 struct kwcpu_registers {
128 u32 config; /*0x20100 */
129 u32 ctrl_stat; /*0x20104 */
130 u32 rstoutn_mask; /* 0x20108 */
131 u32 sys_soft_rst; /* 0x2010C */
132 u32 ahb_mbus_cause_irq; /* 0x20110 */
133 u32 ahb_mbus_mask_irq; /* 0x20114 */
135 u32 ftdll_config; /* 0x20120 */
137 u32 l2_cfg; /* 0x20128 */
142 * Ref: Datasheet sec:A.19
144 struct kwgpio_registers {
158 void reset_cpu(unsigned long ignored);
159 unsigned char get_random_hex(void);
160 unsigned int kw_sdram_bar(enum memory_bank bank);
161 unsigned int kw_sdram_bs(enum memory_bank bank);
162 int kw_config_adr_windows(void);
163 void kw_config_gpio(unsigned int gpp0_oe_val, unsigned int gpp1_oe_val,
164 unsigned int gpp0_oe, unsigned int gpp1_oe);
165 int kw_config_mpp(unsigned int mpp0_7, unsigned int mpp8_15,
166 unsigned int mpp16_23, unsigned int mpp24_31,
167 unsigned int mpp32_39, unsigned int mpp40_47,
168 unsigned int mpp48_55);
169 unsigned int kw_winctrl_calcsize(unsigned int sizeval);
170 #endif /* __ASSEMBLY__ */
171 #endif /* _KWCPU_H */