2 * SPDX-License-Identifier: GPL-2.0+
7 #define KS8695_SDRAM_START 0x00000000
8 #define KS8695_SDRAM_SIZE 0x01000000
9 #define KS8695_MEM_SIZE KS8695_SDRAM_SIZE
10 #define KS8695_MEM_START KS8695_SDRAM_START
12 #define KS8695_PCMCIA_IO_BASE 0x03800000
13 #define KS8695_PCMCIA_IO_SIZE 0x00040000
15 #define KS8695_IO_BASE 0x03FF0000
16 #define KS8695_IO_SIZE 0x00010000
18 #define KS8695_SYSTEN_CONFIG 0x00
19 #define KS8695_SYSTEN_BUS_CLOCK 0x04
21 #define KS8695_FLASH_START 0x02800000
22 #define KS8695_FLASH_SIZE 0x00400000
24 /*i/o control registers offset difinitions*/
25 #define KS8695_IO_CTRL0 0x4000
26 #define KS8695_IO_CTRL1 0x4004
27 #define KS8695_IO_CTRL2 0x4008
28 #define KS8695_IO_CTRL3 0x400C
30 /*memory control registers offset difinitions*/
31 #define KS8695_MEM_CTRL0 0x4010
32 #define KS8695_MEM_CTRL1 0x4014
33 #define KS8695_MEM_CTRL2 0x4018
34 #define KS8695_MEM_CTRL3 0x401C
35 #define KS8695_MEM_GENERAL 0x4020
36 #define KS8695_SDRAM_CTRL0 0x4030
37 #define KS8695_SDRAM_CTRL1 0x4034
38 #define KS8695_SDRAM_GENERAL 0x4038
39 #define KS8695_SDRAM_BUFFER 0x403C
40 #define KS8695_SDRAM_REFRESH 0x4040
42 /*WAN control registers offset difinitions*/
43 #define KS8695_WAN_DMA_TX 0x6000
44 #define KS8695_WAN_DMA_RX 0x6004
45 #define KS8695_WAN_DMA_TX_START 0x6008
46 #define KS8695_WAN_DMA_RX_START 0x600C
47 #define KS8695_WAN_TX_LIST 0x6010
48 #define KS8695_WAN_RX_LIST 0x6014
49 #define KS8695_WAN_MAC_LOW 0x6018
50 #define KS8695_WAN_MAC_HIGH 0x601C
51 #define KS8695_WAN_MAC_ELOW 0x6080
52 #define KS8695_WAN_MAC_EHIGH 0x6084
54 /*LAN control registers offset difinitions*/
55 #define KS8695_LAN_DMA_TX 0x8000
56 #define KS8695_LAN_DMA_RX 0x8004
57 #define KS8695_LAN_DMA_TX_START 0x8008
58 #define KS8695_LAN_DMA_RX_START 0x800C
59 #define KS8695_LAN_TX_LIST 0x8010
60 #define KS8695_LAN_RX_LIST 0x8014
61 #define KS8695_LAN_MAC_LOW 0x8018
62 #define KS8695_LAN_MAC_HIGH 0x801C
63 #define KS8695_LAN_MAC_ELOW 0X8080
64 #define KS8695_LAN_MAC_EHIGH 0X8084
66 /*HPNA control registers offset difinitions*/
67 #define KS8695_HPNA_DMA_TX 0xA000
68 #define KS8695_HPNA_DMA_RX 0xA004
69 #define KS8695_HPNA_DMA_TX_START 0xA008
70 #define KS8695_HPNA_DMA_RX_START 0xA00C
71 #define KS8695_HPNA_TX_LIST 0xA010
72 #define KS8695_HPNA_RX_LIST 0xA014
73 #define KS8695_HPNA_MAC_LOW 0xA018
74 #define KS8695_HPNA_MAC_HIGH 0xA01C
75 #define KS8695_HPNA_MAC_ELOW 0xA080
76 #define KS8695_HPNA_MAC_EHIGH 0xA084
78 /*UART control registers offset difinitions*/
79 #define KS8695_UART_RX_BUFFER 0xE000
80 #define KS8695_UART_TX_HOLDING 0xE004
82 #define KS8695_UART_FIFO_CTRL 0xE008
83 #define KS8695_UART_FIFO_TRIG01 0x00
84 #define KS8695_UART_FIFO_TRIG04 0x80
85 #define KS8695_UART_FIFO_TXRST 0x03
86 #define KS8695_UART_FIFO_RXRST 0x02
87 #define KS8695_UART_FIFO_FEN 0x01
89 #define KS8695_UART_LINE_CTRL 0xE00C
90 #define KS8695_UART_LINEC_BRK 0x40
91 #define KS8695_UART_LINEC_EPS 0x10
92 #define KS8695_UART_LINEC_PEN 0x08
93 #define KS8695_UART_LINEC_STP2 0x04
94 #define KS8695_UART_LINEC_WLEN8 0x03
95 #define KS8695_UART_LINEC_WLEN7 0x02
96 #define KS8695_UART_LINEC_WLEN6 0x01
97 #define KS8695_UART_LINEC_WLEN5 0x00
99 #define KS8695_UART_MODEM_CTRL 0xE010
100 #define KS8695_UART_MODEMC_RTS 0x02
101 #define KS8695_UART_MODEMC_DTR 0x01
103 #define KS8695_UART_LINE_STATUS 0xE014
104 #define KS8695_UART_LINES_TXFE 0x20
105 #define KS8695_UART_LINES_BE 0x10
106 #define KS8695_UART_LINES_FE 0x08
107 #define KS8695_UART_LINES_PE 0x04
108 #define KS8695_UART_LINES_OE 0x02
109 #define KS8695_UART_LINES_RXFE 0x01
110 #define KS8695_UART_LINES_ANY (KS8695_UART_LINES_OE|KS8695_UART_LINES_BE|KS8695_UART_LINES_PE|KS8695_UART_LINES_FE)
112 #define KS8695_UART_MODEM_STATUS 0xE018
113 #define KS8695_UART_MODEM_DCD 0x80
114 #define KS8695_UART_MODEM_DSR 0x20
115 #define KS8695_UART_MODEM_CTS 0x10
116 #define KS8695_UART_MODEM_DDCD 0x08
117 #define KS8695_UART_MODEM_DDSR 0x02
118 #define KS8695_UART_MODEM_DCTS 0x01
119 #define UART8695_MODEM_ANY 0xFF
121 #define KS8695_UART_DIVISOR 0xE01C
122 #define KS8695_UART_STATUS 0xE020
124 /*Interrupt controlller registers offset difinitions*/
125 #define KS8695_INT_CONTL 0xE200
126 #define KS8695_INT_ENABLE 0xE204
127 #define KS8695_INT_ENABLE_MODEM 0x0800
128 #define KS8695_INT_ENABLE_ERR 0x0400
129 #define KS8695_INT_ENABLE_RX 0x0200
130 #define KS8695_INT_ENABLE_TX 0x0100
132 #define KS8695_INT_STATUS 0xE208
133 #define KS8695_INT_WAN_PRIORITY 0xE20C
134 #define KS8695_INT_HPNA_PRIORITY 0xE210
135 #define KS8695_INT_LAN_PRIORITY 0xE214
136 #define KS8695_INT_TIMER_PRIORITY 0xE218
137 #define KS8695_INT_UART_PRIORITY 0xE21C
138 #define KS8695_INT_EXT_PRIORITY 0xE220
139 #define KS8695_INT_CHAN_PRIORITY 0xE224
140 #define KS8695_INT_BUSERROR_PRO 0xE228
141 #define KS8695_INT_MASK_STATUS 0xE22C
142 #define KS8695_FIQ_PEND_PRIORITY 0xE230
143 #define KS8695_IRQ_PEND_PRIORITY 0xE234
145 /*timer registers offset difinitions*/
146 #define KS8695_TIMER_CTRL 0xE400
147 #define KS8695_TIMER1 0xE404
148 #define KS8695_TIMER0 0xE408
149 #define KS8695_TIMER1_PCOUNT 0xE40C
150 #define KS8695_TIMER0_PCOUNT 0xE410
152 /*GPIO registers offset difinitions*/
153 #define KS8695_GPIO_MODE 0xE600
154 #define KS8695_GPIO_CTRL 0xE604
155 #define KS8695_GPIO_DATA 0xE608
157 /*SWITCH registers offset difinitions*/
158 #define KS8695_SWITCH_CTRL0 0xE800
159 #define KS8695_SWITCH_CTRL1 0xE804
160 #define KS8695_SWITCH_PORT1 0xE808
161 #define KS8695_SWITCH_PORT2 0xE80C
162 #define KS8695_SWITCH_PORT3 0xE810
163 #define KS8695_SWITCH_PORT4 0xE814
164 #define KS8695_SWITCH_PORT5 0xE818
165 #define KS8695_SWITCH_AUTO0 0xE81C
166 #define KS8695_SWITCH_AUTO1 0xE820
167 #define KS8695_SWITCH_LUE_CTRL 0xE824
168 #define KS8695_SWITCH_LUE_HIGH 0xE828
169 #define KS8695_SWITCH_LUE_LOW 0xE82C
170 #define KS8695_SWITCH_ADVANCED 0xE830
172 #define KS8695_SWITCH_LPPM12 0xE874
173 #define KS8695_SWITCH_LPPM34 0xE878
175 /*host communication registers difinitions*/
176 #define KS8695_DSCP_HIGH 0xE834
177 #define KS8695_DSCP_LOW 0xE838
178 #define KS8695_SWITCH_MAC_HIGH 0xE83C
179 #define KS8695_SWITCH_MAC_LOW 0xE840
181 /*miscellaneours registers difinitions*/
182 #define KS8695_MANAGE_COUNTER 0xE844
183 #define KS8695_MANAGE_DATA 0xE848
184 #define KS8695_LAN12_POWERMAGR 0xE84C
185 #define KS8695_LAN34_POWERMAGR 0xE850
187 #define KS8695_DEVICE_ID 0xEA00
188 #define KS8695_REVISION_ID 0xEA04
190 #define KS8695_MISC_CONTROL 0xEA08
191 #define KS8695_WAN_CONTROL 0xEA0C
192 #define KS8695_WAN_POWERMAGR 0xEA10
193 #define KS8695_WAN_PHY_CONTROL 0xEA14
194 #define KS8695_WAN_PHY_STATUS 0xEA18
196 /* bus clock definitions*/
197 #define KS8695_BUS_CLOCK_125MHZ 0x0
198 #define KS8695_BUS_CLOCK_100MHZ 0x1
199 #define KS8695_BUS_CLOCK_62MHZ 0x2
200 #define KS8695_BUS_CLOCK_50MHZ 0x3
201 #define KS8695_BUS_CLOCK_41MHZ 0x4
202 #define KS8695_BUS_CLOCK_33MHZ 0x5
203 #define KS8695_BUS_CLOCK_31MHZ 0x6
204 #define KS8695_BUS_CLOCK_25MHZ 0x7
206 /* -------------------------------------------------------------------------------
207 * definations for IRQ
208 * -------------------------------------------------------------------------------*/
210 #define KS8695_INT_EXT_INT0 2
211 #define KS8695_INT_EXT_INT1 3
212 #define KS8695_INT_EXT_INT2 4
213 #define KS8695_INT_EXT_INT3 5
214 #define KS8695_INT_TIMERINT0 6
215 #define KS8695_INT_TIMERINT1 7
216 #define KS8695_INT_UART_TX 8
217 #define KS8695_INT_UART_RX 9
218 #define KS8695_INT_UART_LINE_ERR 10
219 #define KS8695_INT_UART_MODEMS 11
220 #define KS8695_INT_LAN_STOP_RX 12
221 #define KS8695_INT_LAN_STOP_TX 13
222 #define KS8695_INT_LAN_BUF_RX_STATUS 14
223 #define KS8695_INT_LAN_BUF_TX_STATUS 15
224 #define KS8695_INT_LAN_RX_STATUS 16
225 #define KS8695_INT_LAN_TX_STATUS 17
226 #define KS8695_INT_HPAN_STOP_RX 18
227 #define KS8695_INT_HPNA_STOP_TX 19
228 #define KS8695_INT_HPNA_BUF_RX_STATUS 20
229 #define KS8695_INT_HPNA_BUF_TX_STATUS 21
230 #define KS8695_INT_HPNA_RX_STATUS 22
231 #define KS8695_INT_HPNA_TX_STATUS 23
232 #define KS8695_INT_BUS_ERROR 24
233 #define KS8695_INT_WAN_STOP_RX 25
234 #define KS8695_INT_WAN_STOP_TX 26
235 #define KS8695_INT_WAN_BUF_RX_STATUS 27
236 #define KS8695_INT_WAN_BUF_TX_STATUS 28
237 #define KS8695_INT_WAN_RX_STATUS 29
238 #define KS8695_INT_WAN_TX_STATUS 30
240 #define KS8695_INT_UART KS8695_INT_UART_TX
242 /* -------------------------------------------------------------------------------
243 * Interrupt bit positions
245 * -------------------------------------------------------------------------------
248 #define KS8695_INTMASK_EXT_INT0 ( 1 << KS8695_INT_EXT_INT0 )
249 #define KS8695_INTMASK_EXT_INT1 ( 1 << KS8695_INT_EXT_INT1 )
250 #define KS8695_INTMASK_EXT_INT2 ( 1 << KS8695_INT_EXT_INT2 )
251 #define KS8695_INTMASK_EXT_INT3 ( 1 << KS8695_INT_EXT_INT3 )
252 #define KS8695_INTMASK_TIMERINT0 ( 1 << KS8695_INT_TIMERINT0 )
253 #define KS8695_INTMASK_TIMERINT1 ( 1 << KS8695_INT_TIMERINT1 )
254 #define KS8695_INTMASK_UART_TX ( 1 << KS8695_INT_UART_TX )
255 #define KS8695_INTMASK_UART_RX ( 1 << KS8695_INT_UART_RX )
256 #define KS8695_INTMASK_UART_LINE_ERR ( 1 << KS8695_INT_UART_LINE_ERR )
257 #define KS8695_INTMASK_UART_MODEMS ( 1 << KS8695_INT_UART_MODEMS )
258 #define KS8695_INTMASK_LAN_STOP_RX ( 1 << KS8695_INT_LAN_STOP_RX )
259 #define KS8695_INTMASK_LAN_STOP_TX ( 1 << KS8695_INT_LAN_STOP_TX )
260 #define KS8695_INTMASK_LAN_BUF_RX_STATUS ( 1 << KS8695_INT_LAN_BUF_RX_STATUS )
261 #define KS8695_INTMASK_LAN_BUF_TX_STATUS ( 1 << KS8695_INT_LAN_BUF_TX_STATUS )
262 #define KS8695_INTMASK_LAN_RX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
263 #define KS8695_INTMASK_LAN_TX_STATUS ( 1 << KS8695_INT_LAN_RX_STATUS )
264 #define KS8695_INTMASK_HPAN_STOP_RX ( 1 << KS8695_INT_HPAN_STOP_RX )
265 #define KS8695_INTMASK_HPNA_STOP_TX ( 1 << KS8695_INT_HPNA_STOP_TX )
266 #define KS8695_INTMASK_HPNA_BUF_RX_STATUS ( 1 << KS8695_INT_HPNA_BUF_RX_STATUS )
267 #define KS8695_INTMAKS_HPNA_BUF_TX_STATUS ( 1 << KS8695_INT_HPNA_BUF_TX_STATUS
268 #define KS8695_INTMASK_HPNA_RX_STATUS ( 1 << KS8695_INT_HPNA_RX_STATUS )
269 #define KS8695_INTMASK_HPNA_TX_STATUS ( 1 << KS8695_INT_HPNA_TX_STATUS )
270 #define KS8695_INTMASK_BUS_ERROR ( 1 << KS8695_INT_BUS_ERROR )
271 #define KS8695_INTMASK_WAN_STOP_RX ( 1 << KS8695_INT_WAN_STOP_RX )
272 #define KS8695_INTMASK_WAN_STOP_TX ( 1 << KS8695_INT_WAN_STOP_TX )
273 #define KS8695_INTMASK_WAN_BUF_RX_STATUS ( 1 << KS8695_INT_WAN_BUF_RX_STATUS )
274 #define KS8695_INTMASK_WAN_BUF_TX_STATUS ( 1 << KS8695_INT_WAN_BUF_TX_STATUS )
275 #define KS8695_INTMASK_WAN_RX_STATUS ( 1 << KS8695_INT_WAN_RX_STATUS )
276 #define KS8695_INTMASK_WAN_TX_STATUS ( 1 << KS8695_INT_WAN_TX_STATUS )
278 #define KS8695_SC_VALID_INT 0xFFFFFFFF
285 * (both run at 25MHz).
288 #define TICKS_PER_uSEC 25
290 #define mSEC_10 (mSEC_1 * 10)