2 * Common definitions for LPC32XX board configurations
4 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #ifndef _LPC32XX_CONFIG_H
10 #define _LPC32XX_CONFIG_H
13 /* Basic CPU architecture */
14 #define CONFIG_ARCH_CPU_INIT
16 #define CONFIG_NR_DRAM_BANKS_MAX 2
18 /* UART configuration */
19 #if (CONFIG_SYS_LPC32XX_UART == 1) || (CONFIG_SYS_LPC32XX_UART == 2) || \
20 (CONFIG_SYS_LPC32XX_UART == 7)
21 #if defined(CONFIG_SPL_BUILD)
22 /* SPL images do not support LPC32xx HSUART, UART5 is selected for SPL */
23 #undef CONFIG_SYS_LPC32XX_UART
24 #define CONFIG_SYS_LPC32XX_UART 5
27 #if !defined(CONFIG_LPC32XX_HSUART)
28 #define CONFIG_LPC32XX_HSUART
32 #if defined(CONFIG_SPL_BUILD)
33 #define CONFIG_SYS_NS16550_SERIAL
34 #define CONFIG_SYS_NS16550_REG_SIZE -4
35 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
37 #define CONFIG_SYS_NS16550_COM1 UART3_BASE
38 #define CONFIG_SYS_NS16550_COM2 UART4_BASE
39 #define CONFIG_SYS_NS16550_COM3 UART5_BASE
40 #define CONFIG_SYS_NS16550_COM4 UART6_BASE
43 #if !defined(CONFIG_SYS_NS16550_CLK)
44 #define CONFIG_SYS_NS16550_CLK 13000000
47 #if !defined(CONFIG_LPC32XX_HSUART) || defined(CONFIG_SPL_BUILD)
48 #define CONFIG_CONS_INDEX (CONFIG_SYS_LPC32XX_UART - 2)
50 #define CONFIG_CONS_INDEX CONFIG_SYS_LPC32XX_UART
53 #define CONFIG_SYS_BAUDRATE_TABLE \
54 { 9600, 19200, 38400, 57600, 115200, 230400, 460800 }
57 #define LPC32XX_ETH_BASE ETHERNET_BASE
60 #if defined(CONFIG_NAND_LPC32XX_SLC)
61 #define NAND_LARGE_BLOCK_PAGE_SIZE 0x800
62 #define NAND_SMALL_BLOCK_PAGE_SIZE 0x200
64 #if !defined(CONFIG_SYS_NAND_PAGE_SIZE)
65 #define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
68 #if (CONFIG_SYS_NAND_PAGE_SIZE == NAND_LARGE_BLOCK_PAGE_SIZE)
69 #define CONFIG_SYS_NAND_OOBSIZE 64
70 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
71 48, 49, 50, 51, 52, 53, 54, 55, \
72 56, 57, 58, 59, 60, 61, 62, 63, }
73 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
74 #elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
75 #define CONFIG_SYS_NAND_OOBSIZE 16
76 #define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
77 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
79 #error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
82 #define CONFIG_SYS_NAND_ECCSIZE 0x100
83 #define CONFIG_SYS_NAND_ECCBYTES 3
84 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
85 CONFIG_SYS_NAND_PAGE_SIZE)
86 #endif /* CONFIG_NAND_LPC32XX_SLC */
89 #if defined(CONFIG_SYS_FLASH_CFI)
90 #define CONFIG_FLASH_CFI_DRIVER
91 #define CONFIG_SYS_FLASH_PROTECTION
95 #if defined(CONFIG_USB_OHCI_LPC32XX)
96 #define CONFIG_USB_OHCI_NEW
97 #define CONFIG_SYS_USB_OHCI_CPU_INIT
98 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
99 #define CONFIG_SYS_USB_OHCI_REGS_BASE USB_BASE
100 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "lpc32xx-ohci"
103 #endif /* _LPC32XX_CONFIG_H */