2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_
8 #define __ASM_ARCH_LS102XA_IMMAP_H_
11 #define SVR_MAJ(svr) (((svr) >> 4) & 0xf)
12 #define SVR_MIN(svr) (((svr) >> 0) & 0xf)
13 #define SVR_SOC_VER(svr) (((svr) >> 8) & 0x7ff)
14 #define IS_E_PROCESSOR(svr) (svr & 0x80000)
15 #define IS_SVR_REV(svr, maj, min) \
16 ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
18 #define SOC_VER_SLS1020 0x00
19 #define SOC_VER_LS1020 0x10
20 #define SOC_VER_LS1021 0x11
21 #define SOC_VER_LS1022 0x12
23 #define SOC_MAJOR_VER_1_0 0x1
24 #define SOC_MAJOR_VER_2_0 0x2
26 #define CCSR_BRR_OFFSET 0xe4
27 #define CCSR_SCRATCHRW1_OFFSET 0x200
29 #define RCWSR0_SYS_PLL_RAT_SHIFT 25
30 #define RCWSR0_SYS_PLL_RAT_MASK 0x1f
31 #define RCWSR0_MEM_PLL_RAT_SHIFT 16
32 #define RCWSR0_MEM_PLL_RAT_MASK 0x3f
34 #define RCWSR4_SRDS1_PRTCL_SHIFT 24
35 #define RCWSR4_SRDS1_PRTCL_MASK 0xff000000
37 #define TIMER_COMP_VAL 0xffffffffffffffffull
38 #define ARCH_TIMER_CTRL_ENABLE (1 << 0)
39 #define SYS_COUNTER_CTRL_ENABLE (1 << 24)
41 #define DCFG_CCSR_PORSR1_RCW_MASK 0xff800000
42 #define DCFG_CCSR_PORSR1_RCW_SRC_I2C 0x24800000
44 #define DCFG_DCSR_PORCR1 0
47 * Define default values for some CCSR macros to make header files cleaner
49 * To completely disable CCSR relocation in a board header file, define
50 * CONFIG_SYS_CCSR_DO_NOT_RELOCATE. This will force CONFIG_SYS_CCSRBAR_PHYS
51 * to a value that is the same as CONFIG_SYS_CCSRBAR.
54 #ifdef CONFIG_SYS_CCSRBAR_PHYS
55 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
58 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
59 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
60 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
61 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
64 #ifndef CONFIG_SYS_CCSRBAR
65 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_IMMR
68 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
69 #ifdef CONFIG_PHYS_64BIT
70 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
72 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0
76 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
77 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_IMMR
80 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
81 CONFIG_SYS_CCSRBAR_PHYS_LOW)
84 unsigned long freq_processor[CONFIG_MAX_CPUS];
85 unsigned long freq_systembus;
86 unsigned long freq_ddrbus;
87 unsigned long freq_localbus;
90 /* Device Configuration and Pin Control */
92 u32 porsr1; /* POR status 1 */
93 u32 porsr2; /* POR status 2 */
95 u32 gpporcr1; /* General-purpose POR configuration */
97 u32 dcfg_fusesr; /* Fuse status register */
98 u8 res_02c[0x70-0x2c];
99 u32 devdisr; /* Device disable control */
100 u32 devdisr2; /* Device disable control 2 */
101 u32 devdisr3; /* Device disable control 3 */
102 u32 devdisr4; /* Device disable control 4 */
103 u32 devdisr5; /* Device disable control 5 */
104 u8 res_084[0x94-0x84];
105 u32 coredisru; /* uppper portion for support of 64 cores */
106 u32 coredisrl; /* lower portion for support of 64 cores */
107 u8 res_09c[0xa4-0x9c];
108 u32 svr; /* System version */
109 u8 res_0a8[0xb0-0xa8];
110 u32 rstcr; /* Reset control */
111 u32 rstrqpblsr; /* Reset request preboot loader status */
112 u8 res_0b8[0xc0-0xb8];
113 u32 rstrqmr1; /* Reset request mask */
114 u8 res_0c4[0xc8-0xc4];
115 u32 rstrqsr1; /* Reset request status */
116 u8 res_0cc[0xd4-0xcc];
117 u32 rstrqwdtmrl; /* Reset request WDT mask */
118 u8 res_0d8[0xdc-0xd8];
119 u32 rstrqwdtsrl; /* Reset request WDT status */
120 u8 res_0e0[0xe4-0xe0];
121 u32 brrl; /* Boot release */
122 u8 res_0e8[0x100-0xe8];
123 u32 rcwsr[16]; /* Reset control word status */
124 #define RCW_SB_EN_REG_INDEX 7
125 #define RCW_SB_EN_MASK 0x00200000
126 u8 res_140[0x200-0x140];
127 u32 scratchrw[4]; /* Scratch Read/Write */
128 u8 res_210[0x300-0x210];
129 u32 scratchw1r[4]; /* Scratch Read (Write once) */
130 u8 res_310[0x400-0x310];
132 u8 res_404[0x550-0x404];
134 u8 res_554[0x604-0x554];
137 u8 res_60c[0x740-0x60c]; /* add more registers when needed */
138 u32 tp_ityp[64]; /* Topology Initiator Type Register */
142 } tp_cluster[1]; /* Core Cluster n Topology Register */
143 u8 res_848[0xe60-0x848];
145 u8 res_e60[0xe68-0xe64];
147 u8 res_e68[0xe80-0xe6c];
151 #define SCFG_ETSECDMAMCR_LE_BD_FR 0x00000c00
152 #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
153 #define SCFG_ETSECCMCR_GE2_CLK125 0x04000000
154 #define SCFG_ETSECCMCR_GE0_CLK125 0x00000000
155 #define SCFG_ETSECCMCR_GE1_CLK125 0x08000000
156 #define SCFG_PIXCLKCR_PXCKEN 0x80000000
157 #define SCFG_QSPI_CLKSEL 0xc0100000
158 #define SCFG_SNPCNFGCR_SEC_RD_WR 0xc0000000
159 #define SCFG_SNPCNFGCR_DCU_RD_WR 0x03000000
160 #define SCFG_SNPCNFGCR_SATA_RD_WR 0x00c00000
161 #define SCFG_SNPCNFGCR_USB3_RD_WR 0x00300000
162 #define SCFG_SNPCNFGCR_DBG_RD_WR 0x000c0000
163 #define SCFG_SNPCNFGCR_EDMA_SNP 0x00020000
164 #define SCFG_ENDIANCR_LE 0x80000000
165 #define SCFG_DPSLPCR_WDRR_EN 0x00000001
166 #define SCFG_PMCINTECR_LPUART 0x40000000
167 #define SCFG_PMCINTECR_FTM 0x20000000
168 #define SCFG_PMCINTECR_GPIO 0x10000000
169 #define SCFG_PMCINTECR_IRQ0 0x08000000
170 #define SCFG_PMCINTECR_IRQ1 0x04000000
171 #define SCFG_PMCINTECR_ETSECRXG0 0x00800000
172 #define SCFG_PMCINTECR_ETSECRXG1 0x00400000
173 #define SCFG_PMCINTECR_ETSECERRG0 0x00080000
174 #define SCFG_PMCINTECR_ETSECERRG1 0x00040000
175 #define SCFG_CLUSTERPMCR_WFIL2EN 0x80000000
177 #define SCFG_BASE 0x01570000
178 #define SCFG_USB3PRM1CR 0x070
179 #define SCFG_USB_TXVREFTUNE 0x9
180 #define SCFG_USB_SQRXTUNE_MASK 0x7
181 #define SCFG_USB3PRM2CR 0x074
182 #define SCFG_USB_PCSTXSWINGFULL_MASK 0x0000FE00
183 #define SCFG_USB_PCSTXSWINGFULL_VAL 0x00008E00
185 #define USB_PHY_BASE 0x08510000
186 #define USB_PHY_RX_OVRD_IN_HI 0x200c
187 #define USB_PHY_RX_EQ_VAL_1 0x0000
188 #define USB_PHY_RX_EQ_VAL_2 0x8000
189 #define USB_PHY_RX_EQ_VAL_3 0x8004
190 #define USB_PHY_RX_EQ_VAL_4 0x800C
192 /* Supplemental Configuration Unit */
208 u32 pex1rdmsgpldlsbsr;
209 u32 pex1rdmsgpldmsbsr;
210 u32 pex2rdmsgpldlsbsr;
211 u32 pex2rdmsgpldmsbsr;
281 u32 clkcncsr; /* core cluster n clock control status */
284 u8 res_040[0x7c0]; /* 0x100 */
290 u32 clkpcsr; /* 0xa00 Platform clock domain control/status */
292 u32 pllpgsr; /* 0xc00 Platform PLL General Status */
294 u32 plldgsr; /* 0xc20 DDR PLL General Status */
312 #define SRDS_MAX_LANES 4
313 #define SRDS_MAX_BANK 2
315 #define SRDS_RSTCTL_RST 0x80000000
316 #define SRDS_RSTCTL_RSTDONE 0x40000000
317 #define SRDS_RSTCTL_RSTERR 0x20000000
318 #define SRDS_RSTCTL_SWRST 0x10000000
319 #define SRDS_RSTCTL_SDEN 0x00000020
320 #define SRDS_RSTCTL_SDRST_B 0x00000040
321 #define SRDS_RSTCTL_PLLRST_B 0x00000080
322 #define SRDS_PLLCR0_POFF 0x80000000
323 #define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000
324 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000
325 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000
326 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000
327 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
328 #define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
329 #define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
330 #define SRDS_PLLCR0_PLL_LCK 0x00800000
331 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
332 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
333 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
334 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
335 #define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
336 #define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
337 #define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
338 #define SRDS_PLLCR1_PLL_BWSEL 0x08000000
342 u32 rstctl; /* Reset Control Register */
344 u32 pllcr0; /* PLL Control Register 0 */
346 u32 pllcr1; /* PLL Control Register 1 */
347 u32 res_0c; /* 0x00c */
350 u8 res_18[0x20-0x18];
352 u8 res_40[0x90-0x40];
353 u32 srdstcalcr; /* 0x90 TX Calibration Control */
354 u8 res_94[0xa0-0x94];
355 u32 srdsrcalcr; /* 0xa0 RX Calibration Control */
356 u8 res_a4[0xb0-0xa4];
357 u32 srdsgr0; /* 0xb0 General Register 0 */
358 u8 res_b4[0xe0-0xb4];
359 u32 srdspccr0; /* 0xe0 Protocol Converter Config 0 */
360 u32 srdspccr1; /* 0xe4 Protocol Converter Config 1 */
361 u32 srdspccr2; /* 0xe8 Protocol Converter Config 2 */
362 u32 srdspccr3; /* 0xec Protocol Converter Config 3 */
363 u32 srdspccr4; /* 0xf0 Protocol Converter Config 4 */
364 u8 res_f4[0x100-0xf4];
366 u32 lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
367 u8 res_104[0x120-0x104];
369 u8 res_180[0x300-0x180];
371 u32 srdspexeqpcr[11];
372 u8 res_330[0x400-0x330];
374 u8 res_404[0x440-0x404];
376 u8 res_444[0x800-0x444];
378 u32 gcr0; /* 0x800 General Control Register 0 */
379 u32 gcr1; /* 0x804 General Control Register 1 */
380 u32 gcr2; /* 0x808 General Control Register 2 */
382 u32 recr0; /* 0x810 Receive Equalization Control */
384 u32 tecr0; /* 0x818 Transmit Equalization Control */
386 u32 ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
387 u8 res_824[0x83c-0x824];
389 } lane[4]; /* Lane A, B, C, D, E, F, G, H */
390 u8 res_a00[0x1000-0xa00]; /* from 0xa00 to 0xfff */
395 /* AHCI (sata) register map */
397 u32 res1[0xa4/4]; /* 0x0 - 0xa4 */
398 u32 pcfg; /* port config */
399 u32 ppcfg; /* port phy1 config */
400 u32 pp2c; /* port phy2 config */
401 u32 pp3c; /* port phy3 config */
402 u32 pp4c; /* port phy4 config */
403 u32 pp5c; /* port phy5 config */
404 u32 paxic; /* port AXI config */
405 u32 axicc; /* AXI cache control */
406 u32 axipc; /* AXI PROT control */
407 u32 ptc; /* port Trans Config */
408 u32 pts; /* port Trans Status */
409 u32 plc; /* port link config */
410 u32 plc1; /* port link config1 */
411 u32 plc2; /* port link config2 */
412 u32 pls; /* port link status */
413 u32 pls1; /* port link status1 */
414 u32 pcmdc; /* port CMD config */
415 u32 ppcs; /* port phy control status */
416 u32 pberr; /* port 0/1 BIST error */
417 u32 cmds; /* port 0/1 CMD status error */
420 #define RCPM_POWMGTCSR 0x130
421 #define RCPM_POWMGTCSR_SERDES_PW 0x80000000
422 #define RCPM_POWMGTCSR_LPM20_REQ 0x00100000
423 #define RCPM_POWMGTCSR_LPM20_ST 0x00000200
424 #define RCPM_POWMGTCSR_P_LPM20_ST 0x00000100
425 #define RCPM_IPPDEXPCR0 0x140
426 #define RCPM_IPPDEXPCR0_ETSEC 0x80000000
427 #define RCPM_IPPDEXPCR0_GPIO 0x00000040
428 #define RCPM_IPPDEXPCR1 0x144
429 #define RCPM_IPPDEXPCR1_LPUART 0x40000000
430 #define RCPM_IPPDEXPCR1_FLEXTIMER 0x20000000
431 #define RCPM_IPPDEXPCR1_OCRAM1 0x10000000
432 #define RCPM_NFIQOUTR 0x15c
433 #define RCPM_NIRQOUTR 0x16c
434 #define RCPM_DSIMSKR 0x18c
435 #define RCPM_CLPCL10SETR 0x1c4
436 #define RCPM_CLPCL10SETR_C0 0x00000001
458 #endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */