git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_
   8 #define __ASM_ARCH_LS102XA_IMMAP_H_
   9
  10 #define SVR_MAJ(svr)            (((svr) >>  4) & 0xf)
  11 #define SVR_MIN(svr)            (((svr) >>  0) & 0xf)
  12 #define SVR_SOC_VER(svr)        (((svr) >> 8) & 0x7ff)
  13 #define IS_E_PROCESSOR(svr)     (svr & 0x80000)
  14 #define IS_SVR_REV(svr, maj, min) \
  15                 ((SVR_MAJ(svr) == maj) && (SVR_MIN(svr) == min))
  16
  17 #define SOC_VER_SLS1020         0x00
  18 #define SOC_VER_LS1020          0x10
  19 #define SOC_VER_LS1021          0x11
  20 #define SOC_VER_LS1022          0x12
  21
  22 #define SOC_MAJOR_VER_1_0       0x1
  23 #define SOC_MAJOR_VER_2_0       0x2
  24
  25 #define CCSR_BRR_OFFSET         0xe4
  26 #define CCSR_SCRATCHRW1_OFFSET  0x200
  27
  28 #define RCWSR0_SYS_PLL_RAT_SHIFT        25
  29 #define RCWSR0_SYS_PLL_RAT_MASK         0x1f
  30 #define RCWSR0_MEM_PLL_RAT_SHIFT        16
  31 #define RCWSR0_MEM_PLL_RAT_MASK         0x3f
  32
  33 #define RCWSR4_SRDS1_PRTCL_SHIFT        24
  34 #define RCWSR4_SRDS1_PRTCL_MASK         0xff000000
  35
  36 #define TIMER_COMP_VAL                  0xffffffffffffffffull
  37 #define ARCH_TIMER_CTRL_ENABLE          (1 << 0)
  38 #define SYS_COUNTER_CTRL_ENABLE         (1 << 24)
  39
  40 #define DCFG_CCSR_PORSR1_RCW_MASK       0xff800000
  41 #define DCFG_CCSR_PORSR1_RCW_SRC_I2C    0x24800000
  42
  43 #define DCFG_DCSR_PORCR1                0
  44
  45 /*
  46  * Define default values for some CCSR macros to make header files cleaner
  47  *
  48  * To completely disable CCSR relocation in a board header file, define
  49  * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
  50  * to a value that is the same as CONFIG_SYS_CCSRBAR.
  51  */
  52
  53 #ifdef CONFIG_SYS_CCSRBAR_PHYS
  54 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
  55 #endif
  56
  57 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  58 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
  59 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
  60 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0
  61 #endif
  62
  63 #ifndef CONFIG_SYS_CCSRBAR
  64 #define CONFIG_SYS_CCSRBAR              CONFIG_SYS_IMMR
  65 #endif
  66
  67 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
  68 #ifdef CONFIG_PHYS_64BIT
  69 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0xf
  70 #else
  71 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0
  72 #endif
  73 #endif
  74
  75 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
  76 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_IMMR
  77 #endif
  78
  79 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
  80                                  CONFIG_SYS_CCSRBAR_PHYS_LOW)
  81
  82 struct sys_info {
  83         unsigned long freq_processor[CONFIG_MAX_CPUS];
  84         unsigned long freq_systembus;
  85         unsigned long freq_ddrbus;
  86         unsigned long freq_localbus;
  87 };
  88
  89 /* Device Configuration and Pin Control */
  90 struct ccsr_gur {
  91         u32     porsr1;         /* POR status 1 */
  92         u32     porsr2;         /* POR status 2 */
  93         u8      res_008[0x20-0x8];
  94         u32     gpporcr1;       /* General-purpose POR configuration */
  95         u32     gpporcr2;
  96         u32     dcfg_fusesr;    /* Fuse status register */
  97         u8      res_02c[0x70-0x2c];
  98         u32     devdisr;        /* Device disable control */
  99         u32     devdisr2;       /* Device disable control 2 */
 100         u32     devdisr3;       /* Device disable control 3 */
 101         u32     devdisr4;       /* Device disable control 4 */
 102         u32     devdisr5;       /* Device disable control 5 */
 103         u8      res_084[0x94-0x84];
 104         u32     coredisru;      /* uppper portion for support of 64 cores */
 105         u32     coredisrl;      /* lower portion for support of 64 cores */
 106         u8      res_09c[0xa4-0x9c];
 107         u32     svr;            /* System version */
 108         u8      res_0a8[0xb0-0xa8];
 109         u32     rstcr;          /* Reset control */
 110         u32     rstrqpblsr;     /* Reset request preboot loader status */
 111         u8      res_0b8[0xc0-0xb8];
 112         u32     rstrqmr1;       /* Reset request mask */
 113         u8      res_0c4[0xc8-0xc4];
 114         u32     rstrqsr1;       /* Reset request status */
 115         u8      res_0cc[0xd4-0xcc];
 116         u32     rstrqwdtmrl;    /* Reset request WDT mask */
 117         u8      res_0d8[0xdc-0xd8];
 118         u32     rstrqwdtsrl;    /* Reset request WDT status */
 119         u8      res_0e0[0xe4-0xe0];
 120         u32     brrl;           /* Boot release */
 121         u8      res_0e8[0x100-0xe8];
 122         u32     rcwsr[16];      /* Reset control word status */
 123 #define RCW_SB_EN_REG_INDEX     7
 124 #define RCW_SB_EN_MASK          0x00200000
 125         u8      res_140[0x200-0x140];
 126         u32     scratchrw[4];  /* Scratch Read/Write */
 127         u8      res_210[0x300-0x210];
 128         u32     scratchw1r[4];  /* Scratch Read (Write once) */
 129         u8      res_310[0x400-0x310];
 130         u32     crstsr;
 131         u8      res_404[0x550-0x404];
 132         u32     sataliodnr;
 133         u8      res_554[0x604-0x554];
 134         u32     pamubypenr;
 135         u32     dmacr1;
 136         u8      res_60c[0x740-0x60c];   /* add more registers when needed */
 137         u32     tp_ityp[64];    /* Topology Initiator Type Register */
 138         struct {
 139                 u32     upper;
 140                 u32     lower;
 141         } tp_cluster[1];        /* Core Cluster n Topology Register */
 142         u8      res_848[0xe60-0x848];
 143         u32     ddrclkdr;
 144         u8      res_e60[0xe68-0xe64];
 145         u32     ifcclkdr;
 146         u8      res_e68[0xe80-0xe6c];
 147         u32     sdhcpcr;
 148 };
 149
 150 #define SCFG_ETSECDMAMCR_LE_BD_FR       0x00000c00
 151 #define SCFG_SNPCNFGCR_SEC_RD_WR        0xc0000000
 152 #define SCFG_ETSECCMCR_GE2_CLK125       0x04000000
 153 #define SCFG_ETSECCMCR_GE0_CLK125       0x00000000
 154 #define SCFG_ETSECCMCR_GE1_CLK125       0x08000000
 155 #define SCFG_PIXCLKCR_PXCKEN            0x80000000
 156 #define SCFG_QSPI_CLKSEL                0xc0100000
 157 #define SCFG_SNPCNFGCR_SEC_RD_WR        0xc0000000
 158 #define SCFG_SNPCNFGCR_DCU_RD_WR        0x03000000
 159 #define SCFG_SNPCNFGCR_SATA_RD_WR       0x00c00000
 160 #define SCFG_SNPCNFGCR_USB3_RD_WR       0x00300000
 161 #define SCFG_SNPCNFGCR_DBG_RD_WR        0x000c0000
 162 #define SCFG_SNPCNFGCR_EDMA_SNP         0x00020000
 163 #define SCFG_ENDIANCR_LE                0x80000000
 164 #define SCFG_DPSLPCR_WDRR_EN            0x00000001
 165 #define SCFG_PMCINTECR_LPUART           0x40000000
 166 #define SCFG_PMCINTECR_FTM              0x20000000
 167 #define SCFG_PMCINTECR_GPIO             0x10000000
 168 #define SCFG_PMCINTECR_IRQ0             0x08000000
 169 #define SCFG_PMCINTECR_IRQ1             0x04000000
 170 #define SCFG_PMCINTECR_ETSECRXG0        0x00800000
 171 #define SCFG_PMCINTECR_ETSECRXG1        0x00400000
 172 #define SCFG_PMCINTECR_ETSECERRG0       0x00080000
 173 #define SCFG_PMCINTECR_ETSECERRG1       0x00040000
 174 #define SCFG_CLUSTERPMCR_WFIL2EN        0x80000000
 175
 176 /* Supplemental Configuration Unit */
 177 struct ccsr_scfg {
 178         u32 dpslpcr;
 179         u32 resv0[2];
 180         u32 etsecclkdpslpcr;
 181         u32 resv1[5];
 182         u32 fuseovrdcr;
 183         u32 pixclkcr;
 184         u32 resv2[5];
 185         u32 spimsicr;
 186         u32 resv3[6];
 187         u32 pex1pmwrcr;
 188         u32 pex1pmrdsr;
 189         u32 resv4[3];
 190         u32 usb3prm1cr;
 191         u32 usb4prm2cr;
 192         u32 pex1rdmsgpldlsbsr;
 193         u32 pex1rdmsgpldmsbsr;
 194         u32 pex2rdmsgpldlsbsr;
 195         u32 pex2rdmsgpldmsbsr;
 196         u32 pex1rdmmsgrqsr;
 197         u32 pex2rdmmsgrqsr;
 198         u32 spimsiclrcr;
 199         u32 pexmscportsr[2];
 200         u32 pex2pmwrcr;
 201         u32 resv5[24];
 202         u32 mac1_streamid;
 203         u32 mac2_streamid;
 204         u32 mac3_streamid;
 205         u32 pex1_streamid;
 206         u32 pex2_streamid;
 207         u32 dma_streamid;
 208         u32 sata_streamid;
 209         u32 usb3_streamid;
 210         u32 qe_streamid;
 211         u32 sdhc_streamid;
 212         u32 adma_streamid;
 213         u32 letechsftrstcr;
 214         u32 core0_sft_rst;
 215         u32 core1_sft_rst;
 216         u32 resv6[1];
 217         u32 usb_hi_addr;
 218         u32 etsecclkadjcr;
 219         u32 sai_clk;
 220         u32 resv7[1];
 221         u32 dcu_streamid;
 222         u32 usb2_streamid;
 223         u32 ftm_reset;
 224         u32 altcbar;
 225         u32 qspi_cfg;
 226         u32 pmcintecr;
 227         u32 pmcintlecr;
 228         u32 pmcintsr;
 229         u32 qos1;
 230         u32 qos2;
 231         u32 qos3;
 232         u32 cci_cfg;
 233         u32 endiancr;
 234         u32 etsecdmamcr;
 235         u32 usb3prm3cr;
 236         u32 resv9[1];
 237         u32 debug_streamid;
 238         u32 resv10[5];
 239         u32 snpcnfgcr;
 240         u32 hrstcr;
 241         u32 intpcr;
 242         u32 resv12[20];
 243         u32 scfgrevcr;
 244         u32 coresrencr;
 245         u32 pex2pmrdsr;
 246         u32 eddrtqcfg;
 247         u32 ddrc2cr;
 248         u32 ddrc3cr;
 249         u32 ddrc4cr;
 250         u32 ddrgcr;
 251         u32 resv13[120];
 252         u32 qeioclkcr;
 253         u32 etsecmcr;
 254         u32 sdhciovserlcr;
 255         u32 resv14[61];
 256         u32 sparecr[8];
 257         u32 resv15[248];
 258         u32 core0sftrstsr;
 259         u32 clusterpmcr;
 260 };
 261
 262 /* Clocking */
 263 struct ccsr_clk {
 264         struct {
 265                 u32 clkcncsr;   /* core cluster n clock control status */
 266                 u8  res_004[0x1c];
 267         } clkcsr[2];
 268         u8      res_040[0x7c0]; /* 0x100 */
 269         struct {
 270                 u32 pllcngsr;
 271                 u8 res_804[0x1c];
 272         } pllcgsr[2];
 273         u8      res_840[0x1c0];
 274         u32     clkpcsr;        /* 0xa00 Platform clock domain control/status */
 275         u8      res_a04[0x1fc];
 276         u32     pllpgsr;        /* 0xc00 Platform PLL General Status */
 277         u8      res_c04[0x1c];
 278         u32     plldgsr;        /* 0xc20 DDR PLL General Status */
 279         u8      res_c24[0x3dc];
 280 };
 281
 282 /* System Counter */
 283 struct sctr_regs {
 284         u32 cntcr;
 285         u32 cntsr;
 286         u32 cntcv1;
 287         u32 cntcv2;
 288         u32 resv1[4];
 289         u32 cntfid0;
 290         u32 cntfid1;
 291         u32 resv2[1002];
 292         u32 counterid[12];
 293 };
 294
 295 #define MAX_SERDES                      1
 296 #define SRDS_MAX_LANES                  4
 297 #define SRDS_MAX_BANK                   2
 298
 299 #define SRDS_RSTCTL_RST                 0x80000000
 300 #define SRDS_RSTCTL_RSTDONE             0x40000000
 301 #define SRDS_RSTCTL_RSTERR              0x20000000
 302 #define SRDS_RSTCTL_SWRST               0x10000000
 303 #define SRDS_RSTCTL_SDEN                0x00000020
 304 #define SRDS_RSTCTL_SDRST_B             0x00000040
 305 #define SRDS_RSTCTL_PLLRST_B            0x00000080
 306 #define SRDS_PLLCR0_POFF                0x80000000
 307 #define SRDS_PLLCR0_RFCK_SEL_MASK       0x70000000
 308 #define SRDS_PLLCR0_RFCK_SEL_100        0x00000000
 309 #define SRDS_PLLCR0_RFCK_SEL_125        0x10000000
 310 #define SRDS_PLLCR0_RFCK_SEL_156_25     0x20000000
 311 #define SRDS_PLLCR0_RFCK_SEL_150        0x30000000
 312 #define SRDS_PLLCR0_RFCK_SEL_161_13     0x40000000
 313 #define SRDS_PLLCR0_RFCK_SEL_122_88     0x50000000
 314 #define SRDS_PLLCR0_PLL_LCK             0x00800000
 315 #define SRDS_PLLCR0_FRATE_SEL_MASK      0x000f0000
 316 #define SRDS_PLLCR0_FRATE_SEL_5         0x00000000
 317 #define SRDS_PLLCR0_FRATE_SEL_3_75      0x00050000
 318 #define SRDS_PLLCR0_FRATE_SEL_5_15      0x00060000
 319 #define SRDS_PLLCR0_FRATE_SEL_4         0x00070000
 320 #define SRDS_PLLCR0_FRATE_SEL_3_12      0x00090000
 321 #define SRDS_PLLCR0_FRATE_SEL_3         0x000a0000
 322 #define SRDS_PLLCR1_PLL_BWSEL           0x08000000
 323
 324 struct ccsr_serdes {
 325         struct {
 326                 u32     rstctl; /* Reset Control Register */
 327
 328                 u32     pllcr0; /* PLL Control Register 0 */
 329
 330                 u32     pllcr1; /* PLL Control Register 1 */
 331                 u32     res_0c; /* 0x00c */
 332                 u32     pllcr3;
 333                 u32     pllcr4;
 334                 u8      res_18[0x20-0x18];
 335         } bank[2];
 336         u8      res_40[0x90-0x40];
 337         u32     srdstcalcr;     /* 0x90 TX Calibration Control */
 338         u8      res_94[0xa0-0x94];
 339         u32     srdsrcalcr;     /* 0xa0 RX Calibration Control */
 340         u8      res_a4[0xb0-0xa4];
 341         u32     srdsgr0;        /* 0xb0 General Register 0 */
 342         u8      res_b4[0xe0-0xb4];
 343         u32     srdspccr0;      /* 0xe0 Protocol Converter Config 0 */
 344         u32     srdspccr1;      /* 0xe4 Protocol Converter Config 1 */
 345         u32     srdspccr2;      /* 0xe8 Protocol Converter Config 2 */
 346         u32     srdspccr3;      /* 0xec Protocol Converter Config 3 */
 347         u32     srdspccr4;      /* 0xf0 Protocol Converter Config 4 */
 348         u8      res_f4[0x100-0xf4];
 349         struct {
 350                 u32     lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
 351                 u8      res_104[0x120-0x104];
 352         } srdslnpssr[4];
 353         u8      res_180[0x300-0x180];
 354         u32     srdspexeqcr;
 355         u32     srdspexeqpcr[11];
 356         u8      res_330[0x400-0x330];
 357         u32     srdspexapcr;
 358         u8      res_404[0x440-0x404];
 359         u32     srdspexbpcr;
 360         u8      res_444[0x800-0x444];
 361         struct {
 362                 u32     gcr0;   /* 0x800 General Control Register 0 */
 363                 u32     gcr1;   /* 0x804 General Control Register 1 */
 364                 u32     gcr2;   /* 0x808 General Control Register 2 */
 365                 u32     sscr0;
 366                 u32     recr0;  /* 0x810 Receive Equalization Control */
 367                 u32     recr1;
 368                 u32     tecr0;  /* 0x818 Transmit Equalization Control */
 369                 u32     sscr1;
 370                 u32     ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
 371                 u8      res_824[0x83c-0x824];
 372                 u32     tcsr3;
 373         } lane[4];      /* Lane A, B, C, D, E, F, G, H */
 374         u8      res_a00[0x1000-0xa00];  /* from 0xa00 to 0xfff */
 375 };
 376
 377 #define CCI400_CTRLORD_TERM_BARRIER     0x00000008
 378 #define CCI400_CTRLORD_EN_BARRIER       0
 379 #define CCI400_SHAORD_NON_SHAREABLE     0x00000002
 380 #define CCI400_DVM_MESSAGE_REQ_EN       0x00000002
 381 #define CCI400_SNOOP_REQ_EN             0x00000001
 382
 383 /* CCI-400 registers */
 384 struct ccsr_cci400 {
 385         u32 ctrl_ord;                   /* Control Override */
 386         u32 spec_ctrl;                  /* Speculation Control */
 387         u32 secure_access;              /* Secure Access */
 388         u32 status;                     /* Status */
 389         u32 impr_err;                   /* Imprecise Error */
 390         u8 res_14[0x100 - 0x14];
 391         u32 pmcr;                       /* Performance Monitor Control */
 392         u8 res_104[0xfd0 - 0x104];
 393         u32 pid[8];                     /* Peripheral ID */
 394         u32 cid[4];                     /* Component ID */
 395         struct {
 396                 u32 snoop_ctrl;         /* Snoop Control */
 397                 u32 sha_ord;            /* Shareable Override */
 398                 u8 res_1008[0x1100 - 0x1008];
 399                 u32 rc_qos_ord;         /* read channel QoS Value Override */
 400                 u32 wc_qos_ord;         /* read channel QoS Value Override */
 401                 u8 res_1108[0x110c - 0x1108];
 402                 u32 qos_ctrl;           /* QoS Control */
 403                 u32 max_ot;             /* Max OT */
 404                 u8 res_1114[0x1130 - 0x1114];
 405                 u32 target_lat;         /* Target Latency */
 406                 u32 latency_regu;       /* Latency Regulation */
 407                 u32 qos_range;          /* QoS Range */
 408                 u8 res_113c[0x2000 - 0x113c];
 409         } slave[5];                     /* Slave Interface */
 410         u8 res_6000[0x9004 - 0x6000];
 411         u32 cycle_counter;              /* Cycle counter */
 412         u32 count_ctrl;                 /* Count Control */
 413         u32 overflow_status;            /* Overflow Flag Status */
 414         u8 res_9010[0xa000 - 0x9010];
 415         struct {
 416                 u32 event_select;       /* Event Select */
 417                 u32 event_count;        /* Event Count */
 418                 u32 counter_ctrl;       /* Counter Control */
 419                 u32 overflow_status;    /* Overflow Flag Status */
 420                 u8 res_a010[0xb000 - 0xa010];
 421         } pcounter[4];                  /* Performance Counter */
 422         u8 res_e004[0x10000 - 0xe004];
 423 };
 424
 425 /* AHCI (sata) register map */
 426 struct ccsr_ahci {
 427         u32 res1[0xa4/4];       /* 0x0 - 0xa4 */
 428         u32 pcfg;       /* port config */
 429         u32 ppcfg;      /* port phy1 config */
 430         u32 pp2c;       /* port phy2 config */
 431         u32 pp3c;       /* port phy3 config */
 432         u32 pp4c;       /* port phy4 config */
 433         u32 pp5c;       /* port phy5 config */
 434         u32 paxic;      /* port AXI config */
 435         u32 axicc;      /* AXI cache control */
 436         u32 axipc;      /* AXI PROT control */
 437         u32 ptc;        /* port Trans Config */
 438         u32 pts;        /* port Trans Status */
 439         u32 plc;        /* port link config */
 440         u32 plc1;       /* port link config1 */
 441         u32 plc2;       /* port link config2 */
 442         u32 pls;        /* port link status */
 443         u32 pls1;       /* port link status1 */
 444         u32 pcmdc;      /* port CMD config */
 445         u32 ppcs;       /* port phy control status */
 446         u32 pberr;      /* port 0/1 BIST error */
 447         u32 cmds;       /* port 0/1 CMD status error */
 448 };
 449
 450 #define RCPM_POWMGTCSR                  0x130
 451 #define RCPM_POWMGTCSR_SERDES_PW        0x80000000
 452 #define RCPM_POWMGTCSR_LPM20_REQ        0x00100000
 453 #define RCPM_POWMGTCSR_LPM20_ST         0x00000200
 454 #define RCPM_POWMGTCSR_P_LPM20_ST       0x00000100
 455 #define RCPM_IPPDEXPCR0                 0x140
 456 #define RCPM_IPPDEXPCR0_ETSEC           0x80000000
 457 #define RCPM_IPPDEXPCR0_GPIO            0x00000040
 458 #define RCPM_IPPDEXPCR1                 0x144
 459 #define RCPM_IPPDEXPCR1_LPUART          0x40000000
 460 #define RCPM_IPPDEXPCR1_FLEXTIMER       0x20000000
 461 #define RCPM_IPPDEXPCR1_OCRAM1          0x10000000
 462 #define RCPM_NFIQOUTR                   0x15c
 463 #define RCPM_NIRQOUTR                   0x16c
 464 #define RCPM_DSIMSKR                    0x18c
 465 #define RCPM_CLPCL10SETR                0x1c4
 466 #define RCPM_CLPCL10SETR_C0             0x00000001
 467
 468 struct ccsr_rcpm {
 469         u8 rev1[0x4c];
 470         u32 twaitsr;
 471         u8 rev2[0xe0];
 472         u32 powmgtcsr;
 473         u8 rev3[0xc];
 474         u32 ippdexpcr0;
 475         u32 ippdexpcr1;
 476         u8 rev4[0x14];
 477         u32 nfiqoutr;
 478         u8 rev5[0xc];
 479         u32 nirqoutr;
 480         u8 rev6[0x1c];
 481         u32 dsimskr;
 482         u8 rev7[0x34];
 483         u32 clpcl10setr;
 484 };
 485
 486 uint get_svr(void);
 487
 488 #endif  /* __ASM_ARCH_LS102XA_IMMAP_H_ */