git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __ASM_ARCH_LS102XA_IMMAP_H_
   8 #define __ASM_ARCH_LS102XA_IMMAP_H_
   9
  10 #define SVR_MAJ(svr)            (((svr) >>  4) & 0xf)
  11 #define SVR_MIN(svr)            (((svr) >>  0) & 0xf)
  12 #define SVR_SOC_VER(svr)        (((svr) >> 8) & 0x7ff)
  13 #define IS_E_PROCESSOR(svr)     (svr & 0x80000)
  14
  15 #define SOC_VER_SLS1020         0x00
  16 #define SOC_VER_LS1020          0x10
  17 #define SOC_VER_LS1021          0x11
  18 #define SOC_VER_LS1022          0x12
  19
  20 #define SOC_MAJOR_VER_1_0       0x1
  21 #define SOC_MAJOR_VER_2_0       0x2
  22
  23 #define CCSR_BRR_OFFSET         0xe4
  24 #define CCSR_SCRATCHRW1_OFFSET  0x200
  25
  26 #define RCWSR0_SYS_PLL_RAT_SHIFT        25
  27 #define RCWSR0_SYS_PLL_RAT_MASK         0x1f
  28 #define RCWSR0_MEM_PLL_RAT_SHIFT        16
  29 #define RCWSR0_MEM_PLL_RAT_MASK         0x3f
  30
  31 #define RCWSR4_SRDS1_PRTCL_SHIFT        24
  32 #define RCWSR4_SRDS1_PRTCL_MASK         0xff000000
  33
  34 #define TIMER_COMP_VAL                  0xffffffff
  35 #define ARCH_TIMER_CTRL_ENABLE          (1 << 0)
  36 #define SYS_COUNTER_CTRL_ENABLE         (1 << 24)
  37
  38 #define DCFG_CCSR_PORSR1_RCW_MASK       0xff800000
  39 #define DCFG_CCSR_PORSR1_RCW_SRC_I2C    0x24800000
  40
  41 #define DCFG_DCSR_PORCR1                0
  42
  43 /*
  44  * Define default values for some CCSR macros to make header files cleaner
  45  *
  46  * To completely disable CCSR relocation in a board header file, define
  47  * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
  48  * to a value that is the same as CONFIG_SYS_CCSRBAR.
  49  */
  50
  51 #ifdef CONFIG_SYS_CCSRBAR_PHYS
  52 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly."
  53 #endif
  54
  55 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  56 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
  57 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
  58 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0
  59 #endif
  60
  61 #ifndef CONFIG_SYS_CCSRBAR
  62 #define CONFIG_SYS_CCSRBAR              CONFIG_SYS_IMMR
  63 #endif
  64
  65 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
  66 #ifdef CONFIG_PHYS_64BIT
  67 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0xf
  68 #else
  69 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH    0
  70 #endif
  71 #endif
  72
  73 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
  74 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_IMMR
  75 #endif
  76
  77 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
  78                                  CONFIG_SYS_CCSRBAR_PHYS_LOW)
  79
  80 struct sys_info {
  81         unsigned long freq_processor[CONFIG_MAX_CPUS];
  82         unsigned long freq_systembus;
  83         unsigned long freq_ddrbus;
  84         unsigned long freq_localbus;
  85 };
  86
  87 /* Device Configuration and Pin Control */
  88 struct ccsr_gur {
  89         u32     porsr1;         /* POR status 1 */
  90         u32     porsr2;         /* POR status 2 */
  91         u8      res_008[0x20-0x8];
  92         u32     gpporcr1;       /* General-purpose POR configuration */
  93         u32     gpporcr2;
  94         u32     dcfg_fusesr;    /* Fuse status register */
  95         u8      res_02c[0x70-0x2c];
  96         u32     devdisr;        /* Device disable control */
  97         u32     devdisr2;       /* Device disable control 2 */
  98         u32     devdisr3;       /* Device disable control 3 */
  99         u32     devdisr4;       /* Device disable control 4 */
 100         u32     devdisr5;       /* Device disable control 5 */
 101         u8      res_084[0x94-0x84];
 102         u32     coredisru;      /* uppper portion for support of 64 cores */
 103         u32     coredisrl;      /* lower portion for support of 64 cores */
 104         u8      res_09c[0xa4-0x9c];
 105         u32     svr;            /* System version */
 106         u8      res_0a8[0xb0-0xa8];
 107         u32     rstcr;          /* Reset control */
 108         u32     rstrqpblsr;     /* Reset request preboot loader status */
 109         u8      res_0b8[0xc0-0xb8];
 110         u32     rstrqmr1;       /* Reset request mask */
 111         u8      res_0c4[0xc8-0xc4];
 112         u32     rstrqsr1;       /* Reset request status */
 113         u8      res_0cc[0xd4-0xcc];
 114         u32     rstrqwdtmrl;    /* Reset request WDT mask */
 115         u8      res_0d8[0xdc-0xd8];
 116         u32     rstrqwdtsrl;    /* Reset request WDT status */
 117         u8      res_0e0[0xe4-0xe0];
 118         u32     brrl;           /* Boot release */
 119         u8      res_0e8[0x100-0xe8];
 120         u32     rcwsr[16];      /* Reset control word status */
 121         u8      res_140[0x200-0x140];
 122         u32     scratchrw[4];  /* Scratch Read/Write */
 123         u8      res_210[0x300-0x210];
 124         u32     scratchw1r[4];  /* Scratch Read (Write once) */
 125         u8      res_310[0x400-0x310];
 126         u32     crstsr;
 127         u8      res_404[0x550-0x404];
 128         u32     sataliodnr;
 129         u8      res_554[0x604-0x554];
 130         u32     pamubypenr;
 131         u32     dmacr1;
 132         u8      res_60c[0x740-0x60c];   /* add more registers when needed */
 133         u32     tp_ityp[64];    /* Topology Initiator Type Register */
 134         struct {
 135                 u32     upper;
 136                 u32     lower;
 137         } tp_cluster[1];        /* Core Cluster n Topology Register */
 138         u8      res_848[0xe60-0x848];
 139         u32     ddrclkdr;
 140         u8      res_e60[0xe68-0xe64];
 141         u32     ifcclkdr;
 142         u8      res_e68[0xe80-0xe6c];
 143         u32     sdhcpcr;
 144 };
 145
 146 #define SCFG_ETSECDMAMCR_LE_BD_FR       0xf8001a0f
 147 #define SCFG_ETSECCMCR_GE2_CLK125       0x04000000
 148 #define SCFG_ETSECCMCR_GE0_CLK125       0x00000000
 149 #define SCFG_ETSECCMCR_GE1_CLK125       0x08000000
 150 #define SCFG_PIXCLKCR_PXCKEN            0x80000000
 151 #define SCFG_QSPI_CLKSEL                0xc0100000
 152
 153 /* Supplemental Configuration Unit */
 154 struct ccsr_scfg {
 155         u32 dpslpcr;
 156         u32 resv0[2];
 157         u32 etsecclkdpslpcr;
 158         u32 resv1[5];
 159         u32 fuseovrdcr;
 160         u32 pixclkcr;
 161         u32 resv2[5];
 162         u32 spimsicr;
 163         u32 resv3[6];
 164         u32 pex1pmwrcr;
 165         u32 pex1pmrdsr;
 166         u32 resv4[3];
 167         u32 usb3prm1cr;
 168         u32 usb4prm2cr;
 169         u32 pex1rdmsgpldlsbsr;
 170         u32 pex1rdmsgpldmsbsr;
 171         u32 pex2rdmsgpldlsbsr;
 172         u32 pex2rdmsgpldmsbsr;
 173         u32 pex1rdmmsgrqsr;
 174         u32 pex2rdmmsgrqsr;
 175         u32 spimsiclrcr;
 176         u32 pexmscportsr[2];
 177         u32 pex2pmwrcr;
 178         u32 resv5[24];
 179         u32 mac1_streamid;
 180         u32 mac2_streamid;
 181         u32 mac3_streamid;
 182         u32 pex1_streamid;
 183         u32 pex2_streamid;
 184         u32 dma_streamid;
 185         u32 sata_streamid;
 186         u32 usb3_streamid;
 187         u32 qe_streamid;
 188         u32 sdhc_streamid;
 189         u32 adma_streamid;
 190         u32 letechsftrstcr;
 191         u32 core0_sft_rst;
 192         u32 core1_sft_rst;
 193         u32 resv6[1];
 194         u32 usb_hi_addr;
 195         u32 etsecclkadjcr;
 196         u32 sai_clk;
 197         u32 resv7[1];
 198         u32 dcu_streamid;
 199         u32 usb2_streamid;
 200         u32 ftm_reset;
 201         u32 altcbar;
 202         u32 qspi_cfg;
 203         u32 pmcintecr;
 204         u32 pmcintlecr;
 205         u32 pmcintsr;
 206         u32 qos1;
 207         u32 qos2;
 208         u32 qos3;
 209         u32 cci_cfg;
 210         u32 resv8[1];
 211         u32 etsecdmamcr;
 212         u32 usb3prm3cr;
 213         u32 resv9[1];
 214         u32 debug_streamid;
 215         u32 resv10[5];
 216         u32 snpcnfgcr;
 217         u32 resv11[1];
 218         u32 intpcr;
 219         u32 resv12[20];
 220         u32 scfgrevcr;
 221         u32 coresrencr;
 222         u32 pex2pmrdsr;
 223         u32 ddrc1cr;
 224         u32 ddrc2cr;
 225         u32 ddrc3cr;
 226         u32 ddrc4cr;
 227         u32 ddrgcr;
 228         u32 resv13[120];
 229         u32 qeioclkcr;
 230         u32 etsecmcr;
 231         u32 sdhciovserlcr;
 232         u32 resv14[61];
 233         u32 sparecr[8];
 234 };
 235
 236 /* Clocking */
 237 struct ccsr_clk {
 238         struct {
 239                 u32 clkcncsr;   /* core cluster n clock control status */
 240                 u8  res_004[0x1c];
 241         } clkcsr[2];
 242         u8      res_040[0x7c0]; /* 0x100 */
 243         struct {
 244                 u32 pllcngsr;
 245                 u8 res_804[0x1c];
 246         } pllcgsr[2];
 247         u8      res_840[0x1c0];
 248         u32     clkpcsr;        /* 0xa00 Platform clock domain control/status */
 249         u8      res_a04[0x1fc];
 250         u32     pllpgsr;        /* 0xc00 Platform PLL General Status */
 251         u8      res_c04[0x1c];
 252         u32     plldgsr;        /* 0xc20 DDR PLL General Status */
 253         u8      res_c24[0x3dc];
 254 };
 255
 256 /* System Counter */
 257 struct sctr_regs {
 258         u32 cntcr;
 259         u32 cntsr;
 260         u32 cntcv1;
 261         u32 cntcv2;
 262         u32 resv1[4];
 263         u32 cntfid0;
 264         u32 cntfid1;
 265         u32 resv2[1002];
 266         u32 counterid[12];
 267 };
 268
 269 #define MAX_SERDES                      1
 270 #define SRDS_MAX_LANES                  4
 271 #define SRDS_MAX_BANK                   2
 272
 273 #define SRDS_RSTCTL_RST                 0x80000000
 274 #define SRDS_RSTCTL_RSTDONE             0x40000000
 275 #define SRDS_RSTCTL_RSTERR              0x20000000
 276 #define SRDS_RSTCTL_SWRST               0x10000000
 277 #define SRDS_RSTCTL_SDEN                0x00000020
 278 #define SRDS_RSTCTL_SDRST_B             0x00000040
 279 #define SRDS_RSTCTL_PLLRST_B            0x00000080
 280 #define SRDS_PLLCR0_POFF                0x80000000
 281 #define SRDS_PLLCR0_RFCK_SEL_MASK       0x70000000
 282 #define SRDS_PLLCR0_RFCK_SEL_100        0x00000000
 283 #define SRDS_PLLCR0_RFCK_SEL_125        0x10000000
 284 #define SRDS_PLLCR0_RFCK_SEL_156_25     0x20000000
 285 #define SRDS_PLLCR0_RFCK_SEL_150        0x30000000
 286 #define SRDS_PLLCR0_RFCK_SEL_161_13     0x40000000
 287 #define SRDS_PLLCR0_RFCK_SEL_122_88     0x50000000
 288 #define SRDS_PLLCR0_PLL_LCK             0x00800000
 289 #define SRDS_PLLCR0_FRATE_SEL_MASK      0x000f0000
 290 #define SRDS_PLLCR0_FRATE_SEL_5         0x00000000
 291 #define SRDS_PLLCR0_FRATE_SEL_3_75      0x00050000
 292 #define SRDS_PLLCR0_FRATE_SEL_5_15      0x00060000
 293 #define SRDS_PLLCR0_FRATE_SEL_4         0x00070000
 294 #define SRDS_PLLCR0_FRATE_SEL_3_12      0x00090000
 295 #define SRDS_PLLCR0_FRATE_SEL_3         0x000a0000
 296 #define SRDS_PLLCR1_PLL_BWSEL           0x08000000
 297
 298 struct ccsr_serdes {
 299         struct {
 300                 u32     rstctl; /* Reset Control Register */
 301
 302                 u32     pllcr0; /* PLL Control Register 0 */
 303
 304                 u32     pllcr1; /* PLL Control Register 1 */
 305                 u32     res_0c; /* 0x00c */
 306                 u32     pllcr3;
 307                 u32     pllcr4;
 308                 u8      res_18[0x20-0x18];
 309         } bank[2];
 310         u8      res_40[0x90-0x40];
 311         u32     srdstcalcr;     /* 0x90 TX Calibration Control */
 312         u8      res_94[0xa0-0x94];
 313         u32     srdsrcalcr;     /* 0xa0 RX Calibration Control */
 314         u8      res_a4[0xb0-0xa4];
 315         u32     srdsgr0;        /* 0xb0 General Register 0 */
 316         u8      res_b4[0xe0-0xb4];
 317         u32     srdspccr0;      /* 0xe0 Protocol Converter Config 0 */
 318         u32     srdspccr1;      /* 0xe4 Protocol Converter Config 1 */
 319         u32     srdspccr2;      /* 0xe8 Protocol Converter Config 2 */
 320         u32     srdspccr3;      /* 0xec Protocol Converter Config 3 */
 321         u32     srdspccr4;      /* 0xf0 Protocol Converter Config 4 */
 322         u8      res_f4[0x100-0xf4];
 323         struct {
 324                 u32     lnpssr; /* 0x100, 0x120, ..., 0x1e0 */
 325                 u8      res_104[0x120-0x104];
 326         } srdslnpssr[4];
 327         u8      res_180[0x300-0x180];
 328         u32     srdspexeqcr;
 329         u32     srdspexeqpcr[11];
 330         u8      res_330[0x400-0x330];
 331         u32     srdspexapcr;
 332         u8      res_404[0x440-0x404];
 333         u32     srdspexbpcr;
 334         u8      res_444[0x800-0x444];
 335         struct {
 336                 u32     gcr0;   /* 0x800 General Control Register 0 */
 337                 u32     gcr1;   /* 0x804 General Control Register 1 */
 338                 u32     gcr2;   /* 0x808 General Control Register 2 */
 339                 u32     sscr0;
 340                 u32     recr0;  /* 0x810 Receive Equalization Control */
 341                 u32     recr1;
 342                 u32     tecr0;  /* 0x818 Transmit Equalization Control */
 343                 u32     sscr1;
 344                 u32     ttlcr0; /* 0x820 Transition Tracking Loop Ctrl 0 */
 345                 u8      res_824[0x83c-0x824];
 346                 u32     tcsr3;
 347         } lane[4];      /* Lane A, B, C, D, E, F, G, H */
 348         u8      res_a00[0x1000-0xa00];  /* from 0xa00 to 0xfff */
 349 };
 350
 351 #define DDR_SDRAM_CFG                   0x470c0008
 352 #define DDR_CS0_BNDS                    0x008000bf
 353 #define DDR_CS0_CONFIG                  0x80014302
 354 #define DDR_TIMING_CFG_0                0x50550004
 355 #define DDR_TIMING_CFG_1                0xbcb38c56
 356 #define DDR_TIMING_CFG_2                0x0040d120
 357 #define DDR_TIMING_CFG_3                0x010e1000
 358 #define DDR_TIMING_CFG_4                0x00000001
 359 #define DDR_TIMING_CFG_5                0x03401400
 360 #define DDR_SDRAM_CFG_2                 0x00401010
 361 #define DDR_SDRAM_MODE                  0x00061c60
 362 #define DDR_SDRAM_MODE_2                0x00180000
 363 #define DDR_SDRAM_INTERVAL              0x18600618
 364 #define DDR_DDR_WRLVL_CNTL              0x8655f605
 365 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
 366 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
 367 #define DDR_DDR_CDR1                    0x80040000
 368 #define DDR_DDR_CDR2                    0x00000001
 369 #define DDR_SDRAM_CLK_CNTL              0x02000000
 370 #define DDR_DDR_ZQ_CNTL                 0x89080600
 371 #define DDR_CS0_CONFIG_2                0
 372 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
 373
 374 /* DDR memory controller registers */
 375 struct ccsr_ddr {
 376         u32 cs0_bnds;                   /* Chip Select 0 Memory Bounds */
 377         u32 resv1[1];
 378         u32 cs1_bnds;                   /* Chip Select 1 Memory Bounds */
 379         u32 resv2[1];
 380         u32 cs2_bnds;                   /* Chip Select 2 Memory Bounds */
 381         u32 resv3[1];
 382         u32 cs3_bnds;                   /* Chip Select 3 Memory Bounds */
 383         u32 resv4[25];
 384         u32 cs0_config;                 /* Chip Select Configuration */
 385         u32 cs1_config;                 /* Chip Select Configuration */
 386         u32 cs2_config;                 /* Chip Select Configuration */
 387         u32 cs3_config;                 /* Chip Select Configuration */
 388         u32 resv5[12];
 389         u32 cs0_config_2;               /* Chip Select Configuration 2 */
 390         u32 cs1_config_2;               /* Chip Select Configuration 2 */
 391         u32 cs2_config_2;               /* Chip Select Configuration 2 */
 392         u32 cs3_config_2;               /* Chip Select Configuration 2 */
 393         u32 resv6[12];
 394         u32 timing_cfg_3;               /* SDRAM Timing Configuration 3 */
 395         u32 timing_cfg_0;               /* SDRAM Timing Configuration 0 */
 396         u32 timing_cfg_1;               /* SDRAM Timing Configuration 1 */
 397         u32 timing_cfg_2;               /* SDRAM Timing Configuration 2 */
 398         u32 sdram_cfg;                  /* SDRAM Control Configuration */
 399         u32 sdram_cfg_2;                /* SDRAM Control Configuration 2 */
 400         u32 sdram_mode;                 /* SDRAM Mode Configuration */
 401         u32 sdram_mode_2;               /* SDRAM Mode Configuration 2 */
 402         u32 sdram_md_cntl;              /* SDRAM Mode Control */
 403         u32 sdram_interval;             /* SDRAM Interval Configuration */
 404         u32 sdram_data_init;            /* SDRAM Data initialization */
 405         u32 resv7[1];
 406         u32 sdram_clk_cntl;             /* SDRAM Clock Control */
 407         u32 resv8[5];
 408         u32 init_addr;                  /* training init addr */
 409         u32 init_ext_addr;              /* training init extended addr */
 410         u32 resv9[4];
 411         u32 timing_cfg_4;               /* SDRAM Timing Configuration 4 */
 412         u32 timing_cfg_5;               /* SDRAM Timing Configuration 5 */
 413         u32 timing_cfg_6;               /* SDRAM Timing Configuration 6 */
 414         u32 timing_cfg_7;               /* SDRAM Timing Configuration 7 */
 415         u32 ddr_zq_cntl;                /* ZQ calibration control*/
 416         u32 ddr_wrlvl_cntl;             /* write leveling control*/
 417         u32 resv10[1];
 418         u32 ddr_sr_cntr;                /* self refresvh counter */
 419         u32 ddr_sdram_rcw_1;            /* Control Words 1 */
 420         u32 ddr_sdram_rcw_2;            /* Control Words 2 */
 421         u32 resv11[2];
 422         u32 ddr_wrlvl_cntl_2;           /* write leveling control 2 */
 423         u32 ddr_wrlvl_cntl_3;           /* write leveling control 3 */
 424         u32 resv12[2];
 425         u32 ddr_sdram_rcw_3;            /* Control Words 3 */
 426         u32 ddr_sdram_rcw_4;            /* Control Words 4 */
 427         u32 ddr_sdram_rcw_5;            /* Control Words 5 */
 428         u32 ddr_sdram_rcw_6;            /* Control Words 6 */
 429         u32 resv13[20];
 430         u32 sdram_mode_3;               /* SDRAM Mode Configuration 3 */
 431         u32 sdram_mode_4;               /* SDRAM Mode Configuration 4 */
 432         u32 sdram_mode_5;               /* SDRAM Mode Configuration 5 */
 433         u32 sdram_mode_6;               /* SDRAM Mode Configuration 6 */
 434         u32 sdram_mode_7;               /* SDRAM Mode Configuration 7 */
 435         u32 sdram_mode_8;               /* SDRAM Mode Configuration 8 */
 436         u32 sdram_mode_9;               /* SDRAM Mode Configuration 9 */
 437         u32 sdram_mode_10;              /* SDRAM Mode Configuration 10 */
 438         u32 sdram_mode_11;              /* SDRAM Mode Configuration 11 */
 439         u32 sdram_mode_12;              /* SDRAM Mode Configuration 12 */
 440         u32 sdram_mode_13;              /* SDRAM Mode Configuration 13 */
 441         u32 sdram_mode_14;              /* SDRAM Mode Configuration 14 */
 442         u32 sdram_mode_15;              /* SDRAM Mode Configuration 15 */
 443         u32 sdram_mode_16;              /* SDRAM Mode Configuration 16 */
 444         u32 resv14[4];
 445         u32 timing_cfg_8;               /* SDRAM Timing Configuration 8 */
 446         u32 timing_cfg_9;               /* SDRAM Timing Configuration 9 */
 447         u32 resv15[2];
 448         u32 sdram_cfg_3;                /* SDRAM Control Configuration 3 */
 449         u32 resv16[15];
 450         u32 deskew_cntl;                /* SDRAM Deskew Control */
 451         u32 resv17[545];
 452         u32 ddr_dsr1;                   /* Debug Status 1 */
 453         u32 ddr_dsr2;                   /* Debug Status 2 */
 454         u32 ddr_cdr1;                   /* Control Driver 1 */
 455         u32 ddr_cdr2;                   /* Control Driver 2 */
 456         u32 resv18[50];
 457         u32 ip_rev1;                    /* IP Block Revision 1 */
 458         u32 ip_rev2;                    /* IP Block Revision 2 */
 459         u32 eor;                        /* Enhanced Optimization Register */
 460         u32 resv19[63];
 461         u32 mtcr;                       /* Memory Test Control Register */
 462         u32 resv20[7];
 463         u32 mtp1;                       /* Memory Test Pattern 1 */
 464         u32 mtp2;                       /* Memory Test Pattern 2 */
 465         u32 mtp3;                       /* Memory Test Pattern 3 */
 466         u32 mtp4;                       /* Memory Test Pattern 4 */
 467         u32 mtp5;                       /* Memory Test Pattern 5 */
 468         u32 mtp6;                       /* Memory Test Pattern 6 */
 469         u32 mtp7;                       /* Memory Test Pattern 7 */
 470         u32 mtp8;                       /* Memory Test Pattern 8 */
 471         u32 mtp9;                       /* Memory Test Pattern 9 */
 472         u32 mtp10;                      /* Memory Test Pattern 10 */
 473         u32 resv21[6];
 474         u32 ddr_mt_st_ext_addr;         /* Memory Test Start Extended Address */
 475         u32 ddr_mt_st_addr;             /* Memory Test Start Address */
 476         u32 ddr_mt_end_ext_addr;        /* Memory Test End Extended Address */
 477         u32 ddr_mt_end_addr;            /* Memory Test End Address */
 478         u32 resv22[36];
 479         u32 data_err_inject_hi;         /* Data Path Err Injection Mask High */
 480         u32 data_err_inject_lo;         /* Data Path Err Injection Mask Low */
 481         u32 ecc_err_inject;             /* Data Path Err Injection Mask ECC */
 482         u32 resv23[5];
 483         u32 capture_data_hi;            /* Data Path Read Capture High */
 484         u32 capture_data_lo;            /* Data Path Read Capture Low */
 485         u32 capture_ecc;                /* Data Path Read Capture ECC */
 486         u32 resv24[5];
 487         u32 err_detect;                 /* Error Detect */
 488         u32 err_disable;                /* Error Disable */
 489         u32 err_int_en;
 490         u32 capture_attributes;         /* Error Attrs Capture */
 491         u32 capture_address;            /* Error Addr Capture */
 492         u32 capture_ext_address;        /* Error Extended Addr Capture */
 493         u32 err_sbe;                    /* Single-Bit ECC Error Management */
 494         u32 resv25[105];
 495 };
 496
 497 #define CCI400_CTRLORD_TERM_BARRIER     0x00000008
 498 #define CCI400_CTRLORD_EN_BARRIER       0
 499 #define CCI400_SHAORD_NON_SHAREABLE     0x00000002
 500 #define CCI400_DVM_MESSAGE_REQ_EN       0x00000002
 501 #define CCI400_SNOOP_REQ_EN             0x00000001
 502
 503 /* CCI-400 registers */
 504 struct ccsr_cci400 {
 505         u32 ctrl_ord;                   /* Control Override */
 506         u32 spec_ctrl;                  /* Speculation Control */
 507         u32 secure_access;              /* Secure Access */
 508         u32 status;                     /* Status */
 509         u32 impr_err;                   /* Imprecise Error */
 510         u8 res_14[0x100 - 0x14];
 511         u32 pmcr;                       /* Performance Monitor Control */
 512         u8 res_104[0xfd0 - 0x104];
 513         u32 pid[8];                     /* Peripheral ID */
 514         u32 cid[4];                     /* Component ID */
 515         struct {
 516                 u32 snoop_ctrl;         /* Snoop Control */
 517                 u32 sha_ord;            /* Shareable Override */
 518                 u8 res_1008[0x1100 - 0x1008];
 519                 u32 rc_qos_ord;         /* read channel QoS Value Override */
 520                 u32 wc_qos_ord;         /* read channel QoS Value Override */
 521                 u8 res_1108[0x110c - 0x1108];
 522                 u32 qos_ctrl;           /* QoS Control */
 523                 u32 max_ot;             /* Max OT */
 524                 u8 res_1114[0x1130 - 0x1114];
 525                 u32 target_lat;         /* Target Latency */
 526                 u32 latency_regu;       /* Latency Regulation */
 527                 u32 qos_range;          /* QoS Range */
 528                 u8 res_113c[0x2000 - 0x113c];
 529         } slave[5];                     /* Slave Interface */
 530         u8 res_6000[0x9004 - 0x6000];
 531         u32 cycle_counter;              /* Cycle counter */
 532         u32 count_ctrl;                 /* Count Control */
 533         u32 overflow_status;            /* Overflow Flag Status */
 534         u8 res_9010[0xa000 - 0x9010];
 535         struct {
 536                 u32 event_select;       /* Event Select */
 537                 u32 event_count;        /* Event Count */
 538                 u32 counter_ctrl;       /* Counter Control */
 539                 u32 overflow_status;    /* Overflow Flag Status */
 540                 u8 res_a010[0xb000 - 0xa010];
 541         } pcounter[4];                  /* Performance Counter */
 542         u8 res_e004[0x10000 - 0xe004];
 543 };
 544 #endif  /* __ASM_ARCH_LS102XA_IMMAP_H_ */