]> git.sur5r.net Git - u-boot/blob - arch/arm/include/asm/arch-meson/gxbb.h
Merge branch 'master' of git://git.denx.de/u-boot-i2c
[u-boot] / arch / arm / include / asm / arch-meson / gxbb.h
1 /*
2  * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
3  *
4  * SPDX-License-Identifier:     GPL-2.0+
5  */
6
7 #ifndef __GXBB_H__
8 #define __GXBB_H__
9
10 #define GXBB_PERIPHS_BASE       0xc8834400
11 #define GXBB_HIU_BASE           0xc883c000
12 #define GXBB_ETH_BASE           0xc9410000
13
14 /* Peripherals registers */
15 #define GXBB_PERIPHS_ADDR(off)  (GXBB_PERIPHS_BASE + ((off) << 2))
16
17 /* GPIO registers 0 to 6 */
18 #define _GXBB_GPIO_OFF(n)       ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
19 #define GXBB_GPIO_EN(n)         GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 0)
20 #define GXBB_GPIO_IN(n)         GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
21 #define GXBB_GPIO_OUT(n)        GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
22
23 #define GXBB_ETH_REG_0          GXBB_PERIPHS_ADDR(0x50)
24 #define GXBB_ETH_REG_1          GXBB_PERIPHS_ADDR(0x51)
25
26 #define GXBB_ETH_REG_0_PHY_INTF         BIT(0)
27 #define GXBB_ETH_REG_0_TX_PHASE(x)      (((x) & 3) << 5)
28 #define GXBB_ETH_REG_0_TX_RATIO(x)      (((x) & 7) << 7)
29 #define GXBB_ETH_REG_0_PHY_CLK_EN       BIT(10)
30 #define GXBB_ETH_REG_0_CLK_EN           BIT(12)
31
32 /* HIU registers */
33 #define GXBB_HIU_ADDR(off)      (GXBB_HIU_BASE + ((off) << 2))
34
35 #define GXBB_MEM_PD_REG_0       GXBB_HIU_ADDR(0x40)
36
37 /* Ethernet memory power domain */
38 #define GXBB_MEM_PD_REG_0_ETH_MASK      (BIT(2) | BIT(3))
39
40 /* Clock gates */
41 #define GXBB_GCLK_MPEG_0        GXBB_HIU_ADDR(0x50)
42 #define GXBB_GCLK_MPEG_1        GXBB_HIU_ADDR(0x51)
43 #define GXBB_GCLK_MPEG_2        GXBB_HIU_ADDR(0x52)
44 #define GXBB_GCLK_MPEG_OTHER    GXBB_HIU_ADDR(0x53)
45 #define GXBB_GCLK_MPEG_AO       GXBB_HIU_ADDR(0x54)
46
47 #define GXBB_GCLK_MPEG_1_ETH    BIT(3)
48
49 #endif /* __GXBB_H__ */